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LTC6803HG-2#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40
LTC6803-2/LTC6803-4
31
680324fa
APPLICATIONS INFORMATION
Table 18. LTC6803 Failure Mechanism Effect Analysis
SCENARIO EFFECT DESIGN MITIGATION
Cell input open-circuit (random) Power-up sequence at IC inputs Clamp diodes at each pin to V
+
and V
–
(within IC) provide
alternate power path
Cell input open-circuit (random) Differential input voltage overstress Zener diodes across each cell voltage input pair (within IC) limits
stress
Disconnection of a harness between
a group of battery cells and the IC
(in a system of stacked groups)
Loss of supply connection to the IC Separate power may be provided by a local supply
Data link disconnection between
LTC6803 and the master
Loss of serial communication (no stress to ICs) The device will enter standby mode within 2 seconds of
disconnect. Discharge switches are disabled in standby mode
Cell-pack integrity, break between
stacked units
No effect during charge or discharge Use digital isolators to isolate the LTC6803-2/LTC6803-4 serial
port from other LTC6803-2/LTC6803-4 serial ports
Cell-pack integrity, break within
stacked unit
Cell input reverse overstress during discharge Add parallel Schottky diodes across each cell for load-path
redundancy. Diode and connections must handle full operating
current of stack, will limit stress on IC
Cell-pack integrity, break within
stacked unit
Cell input positive overstress during charge Add SCR across each cell for charge-path redundancy. SCR and
connections must handle full charging current of stack, will limit
stress on IC by selection of trigger Zener
Internal Protection Diodes
Each pin of the LTC6803 has protection diodes to help
prevent damage to the internal device structures caused
by external application of voltages beyond the supply rails
as shown in Figure 13. The diodes shown are conventional
silicon diodes with a forward breakdown voltage of 0.5V.
The unlabeled Zener diode structures have a reverse
breakdown characteristic which initially breaks down at
12V then snaps back to a 7V clamping potential. The Zener
diodes labeled Z
CLAMP
are higher voltage devices with an
initial reverse breakdown of 30V snapping back to 25V.
The forward voltage drop of all Zeners is 0.5V. Refer to
this diagram in the event of unpredictable voltage clamp-
ing or current flow. Limiting the current flow at any pin to
±10mA will prevent damage to the IC.
READING EXTERNAL TEMPERATURE PROBES
The LTC6803 includes two channels of ADC input, V
TEMP1
and V
TEMP2
, that are intended to monitor thermistors
(tempco about –4%/°C generally) or diodes (–2.2mV/°C
typical) located within the cell array. Sensors can be
powered directly from V
REF
as shown in Figure 14 (up to
60µA total).
+
+
+
+
+
+
+
V
+
C12
S12
C11
S11
C10
S10
C9
S9
C8
S8
C7
S7
C6
S6
C5
S5
C4
S4
C3
S3
C2
S2
C1
S1
C0
V
–
LTC6803-4
100
NEXT HIGHER GROUP
OF 7 CELLS
NEXT LOWER GROUP
OF 7 CELLS
680324 F12
Figure 12. Monitoring 7 Cells with the LTC6803-4
LTC6803-2/LTC6803-4
32
680324fa
APPLICATIONS INFORMATION
For sensors that require higher drive currents, a buffer
op amp may be used as shown in Figure 15. Power for
the sensor is actually sourced indirectly from the V
REG
pin in this case. Probe loads up to about 1mA maximum
are supported in this configuration. Since V
REF
is shut
down during the LTC6803 idle and shutdown modes, the
thermistor drive is also shut off and thus power dissipa-
tion minimized. Since V
REG
remains always on, the buffer
op amp (LT6000 shown) is selected for its ultralow power
consumption (12µA).
Figure 13. Internal Protection Diodes
Expanding Probe Count
As shown Figure 16, a dual 4:1 multiplexer is used to ex-
pand the general purpose V
TEMP1
and V
TEMP2
ADC inputs
to accept 8 different probe signals. The channel is selected
by setting the general purpose digital outputs GPIO1 and
GPIO2 and the resultant signals are buffered by sections
of the LT6004 micropower dual operational amplifier. The
probe excitation circuitry will vary with probe type and is
not shown here.
Another method of multiple sensor support is possible
without the use of any GPIO pins. If the sensors are PN
diodes and several used in parallel, then the hottest diode
will produce the lowest forward voltage and effectively
establish the input signal to the V
TEMP
input(s). The hottest
diode will therefore dominate the readout from the V
TEMP
inputs that the diodes are connected to. In this scenario,
the specific location or distribution of heat is not known,
but such information may not be important in practice.
Figure 17 shows the basic concept. In any of the sensor
configurations shown, a full-scale cold readout would be
an indication of a failed-open sensor connection to the
LTC6803.
Figure 14. Driving Thermistors Directly from V
REF
Figure 15. Buffering V
REF
for Higher Current Sensors
3
S12
2
C12
1
V
+
4
C11
5
S11
6
C10
Z
CLAMP
LTC6803-4
Z
CLAMP
Z
CLAMP
Z
CLAMP
Z
CLAMP
Z
CLAMP
7
S10
8
C9
9
S9
10
C8
11
S8
12
C7
13
S7
14
C6
15
S6
16
C5
17
S5
18
C4
19
S4
20
C3
21
S3
22
C2
23
S2
24
C1
25
S1
26
27
C0
NOTE: NOT SHOWN ARE PN DIODES TO ALL OTHER PINS FROM PIN 27
V
–
44
CSBI
43
SDO
42
SDI
41
SCKI
40
A3
39
A2
38
A1
37
A0
32
V
REG
V
REF
V
TEMP2
V
TEMP1
31
30
29
36
GPIO2
35
GPIO1
34
WDTB
33
TOS
680324 F13
V
REG
V
REF
V
TEMP2
V
TEMP1
NC
V
–
LTC6803-4
1µF
680324 F14
1µF
100k
NTC
100k 100k
100k
NTC
V
REG
V
REF
V
TEMP2
V
TEMP1
NC
V
–
LTC6803-4
680324 F15
10k
NTC
10k 10k
10k
NTC
–
+
LT6000
LTC6803-2/LTC6803-4
33
680324fa
APPLICATIONS INFORMATION
ADDING CALIBRATION AND FULL-STACK
MEASUREMENTS
The general purpose V
TEMP
ADC inputs may be used to digi-
tize any signals from 0V to 4V with accuracy corresponding
closely with that of the cell 1 ADC input. One useful signal
to provide is a high accuracy voltage reference, such as
3.300V from an LTC6655-3.3. From periodic readings of
this signal, the host software can provide correction of
the LTC6803 readings to improve the accuracy over that
of the internal LTC6803 reference and/or validate ADC
operation. Figure 18 shows a means of selectively pow-
ering an LTC6655-3.3 from the battery stack, under the
control of the GPIO1 output of the LTC6803-2. Since the
operational power of the reference IC would add significant
thermal loading to the LTC6803 if powered from V
REG
, an
external high voltage NPN pass transistor is used to form
a local 4.4V (V
be
below V
REG
) from the battery stack. The
GPIO1 signal controls a PMOS FET switch to activate the
reference when calibration is to be performed. Since GPIO
signals default to logic high in shutdown, the reference
will automatically turn off during idle periods.
Another useful signal is a measure of the total stack poten-
tial. This provides a redundant operational measurement
of the cells in the event of a malfunction in the normal
acquisition process, or as a faster means of monitoring
the entire stack potential. Figure 19 shows how a resis-
tive divider is used to derive a scaled representation of a
full cell group potential. A MOSFET is used to disconnect
Figure 16. Expanding Sensor Count with Multiplexing
Figure 17. Using Diode Sensors as Hot Spot Detectors
6
4 8
7
1
8
3
2
1µF
680324 F16
4
1/2 LT6004
1/2 LT6004
+
–
+
–
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Y0
Y2
Y
Y3
Y1
INH
V
EE
GND
PROBE8
PROBE7
PROBE6
PROBE5
PROBE4
PROBE3
PROBE2
PROBE1
CPO2
GPO1
V
REG
V
TEMP2
V
TEMP1
V
–
V
CC
X2
X1
X
X0
X3
A
B
74HC4052
5
V
REG
V
REF
V
TEMP2
V
TEMP1
NC
V
–
LTC6803-4
200k
680324 F17
200k
GPIO1
35
V
REG
31
V
TEMP1
28
V
–
26
1M
TOP CELL POTENTIAL
Si2351DS 100nF
LTC6803-2
SHDN
V
IN
GND
GND
GND
V
OUT_F
V
OUT_S
GND
1
2
3
4
8
7
6
5
1µF 10µF
680324 F18
LTC6655-3.3
CZT5551
Figure 18. Providing Measurement of Calibration Reference
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40

LTC6803HG-2#PBF

Mfr. #:
Buy LTC6803HG-2#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management Battery Stack Monitor, Addressable SPI
Lifecycle:
New from this manufacturer.
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