LTC6803-2/LTC6803-4
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APPLICATIONS INFORMATION
1MHz, which means the converter is sensitive to noise out
to this frequency. And many SAR converters have much
higher bandwidths—up to 50MHz and beyond. It is pos-
sible to filter the input, but if the converter is multiplexed
to measure several input channels a separate filter will be
required for each channel. A low frequency filter cannot
reside between a multiplexer and an ADC and achieve a
high scan rate across multiple channels. Another conse-
quence of filtering a SAR ADC is that any noise reduction
gained by filtering the input cancels the benefit of having
a high sample rate in the first place, since the filter will
take many conversion cycles to settle.
For a given sample rate, a delta-sigma converter can
achieve excellent noise rejection while settling completely
in a single conversion—something that a filtered SAR con-
verter cannot do. Noise rejection is particularly important
in high voltage switching controllers, where switching
noise will invariably be present in the measured voltage.
Other advantages of delta-sigma converters are that they
are inherently monotonic, meaning they have no missing
codes, and they have excellent DC specifications.
Converter Details
The LTC6803 ADC has a 2nd order delta-sigma modulator
followed by a SINC2, finite impulse response (FIR) digital
filter. The front-end sample rate is 512ksps, which greatly
reduces input filtering requirements. A simple 16kHz,
1-pole filter composed of a 100Ω resistor and a 0.1≤F
capacitor at each input will provide adequate filtering
for most applications. These component values will not
degrade the DC accuracy of the ADC.
Each conversion consists of two phases—an autozero
phase and a measurement phase. The ADC is autozeroed
at each conversion, greatly improving CMRR. The second
half of the conversion is the actual measurement.
Noise Rejection
Figure 25 shows the frequency response of the ADC. The
roll-off follows a SINC2 response, with the first notch at
4kHz. Also shown is the response of a 1 pole, 850Hz filter
(187µs time constant) which has the same integrated
response to wideband noise as the LTC6803 ADC, which
is about 1350Hz. This means that if wideband noise is
applied to the LTC6803 input, the increase in noise seen
at the digital output will be the same as an ADC with a
wide bandwidth (such as a SAR) preceded by a perfect
1350Hz brick wall lowpass filter.
Thus if an analog filter is placed in front of a SAR converter
to achieve the same noise rejection as the LTC6803 ADC,
the SAR will have a slower response to input signals. For
example, a step input applied to the input of the 850Hz
filter will take 1.55ms to settle to 12 bits of precision, while
the LTC6803 ADC settles in a single 1ms conversion cycle.
This also means that very high sample rates do not provide
any additional information because the analog filter limits
the frequency response.
While higher order active filters may provide some im-
provement, their complexity makes them impractical for
high channel count measurements as a single filter would
be required for each input.
Also note that the SINC2 response has a 2nd order roll-
off envelope, providing an additional benefit over a single
pole analog filter.
Figure 25. Noise Filtering of the LTC6803-4 ADC
FILTER GAIN (dB)
FREQUENCY (Hz)
100k10
10
–60
100 1k 10k
0
–10
–20
–30
–40
–50
680324 F25
LTC6803-2/LTC6803-4
38
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PACKAGE DESCRIPTION
G Package
44-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1754 Rev Ø)
G44 SSOP 0607 REV Ø
0.10 – 0.25
(.004 – .010)
0° – 8°
SEATING
PLANE
0.55 – 0.95**
(.022 – .037)
1.25
(.0492)
REF
5.00 – 5.60*
(.197 – .221)
7.40 – 8.20
(.291 – .323)
1 2 3 4
5
6
7
8 9 10 11 12 14 15 16 17 18 19 20 21 2213
44 43 42 41
40
39
38
37 36 35 34 33 31 30 29 28 27 26 25 24 2332
12.50 – 13.10*
(.492 – .516)
2.0
(.079)
MAX
1.65 – 1.85
(.065 – .073)
0.05
(.002)
MIN
0.50
(.01968)
BSC
0.20 – 0.30
(.008 – .012)
TYP
MILLIMETERS
(INCHES)
DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS,
BUT DO INCLUDE MOLD MISMATCH AND ARE MEASURED AT
THE PARTING LINE. MOLD FLASH SHALL NOT EXCEED .15mm PER SIDE
LENGTH OF LEAD FOR SOLDERRING TO A SUBSTRATE
THE MAXIMUM DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSIONS.
DAMBAR PROTRUSIONS DO NOT EXCEED 0.13mm PER SIDE
*
**
NOTE:
1.DRAWING IS NOT A JEDEC OUTLINE
2. CONTROLLING DIMENSION: MILLIMETERS
3. DIMENSIONS ARE IN
4. DRAWING NOT TO SCALE
5. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO
ONE ANOTHER WITHIN 0.08mm AT SEATING PLANE
0.25 ±0.05
PARTING
LINE
0.50
BSC
5.3 – 5.7
7.8 – 8.2
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
1.25 ±0.12
LTC6803-2/LTC6803-4
39
680324fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 08/12 Clarification to UV/OV Operation 15

LTC6803HG-2#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management Battery Stack Monitor, Addressable SPI
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