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MT9V024IA7XTM-DP2

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MT9V024/D
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19
V
AA
(3.3V)
Figure 23. Sequence of Control Voltages at the HDR Gate
Exposure
HDR
Voltage
V1~1.4V
V2~1.2V
V3~1.0V
V4~0.8V
t
1
t
2
t
3
V
AA
(3.3V)
V1~1.4V
V2~1.2V
V3~1.0V
t
1
t
2
t
3
Output
Light Intensity
dV1
dV2
dV3
1/t
1
1/t
22
1/t
3
Figure 24. Sequence of Voltages in a Piecewise Linear Pixel Response
The parameters of the step voltage V_Step, which take
values V1, V2, and V3, directly affect the position of the
knee points in Figure 24.
Light intensities work approximately as a reciprocal of the
partial exposure time. Typically,
t
1 is the longest exposure,
t
2 shorter, and so on. Thus the range of light intensities is
shortest for the first slope, providing the highest sensitivity.
The register settings for V_Step and partial exposures are:
V1 = R0x31, bits 5:0 (Context B: R0x39, bits 5:0)
V2 = R0x32, bits 5:0 (Context B: R0x3A, bits 5:0)
V3 = R0x33, bits 5:0 (Context B: R0x3B, bits 5:0)
V4 = R0x34, bits 5:0 (Context B: R0x3C, bits 5:0)
t
INT
= t
1
+ t
2
+ t
3
There are two ways to specify the knee points timing, the
first by manual setting and the second by automatic knee
point adjustment. Knee point auto adjust is controlled for
context A by R0x0A[8] (where default is ON), and for
context B by R0xD1[8] (where default is OFF ).
When the knee point auto adjust enabler is enabled (set
HIGH), the MT9V024 calculates the knee points
automatically using the following equations:
t
1
+ t
INT
* t
2
* t
3
(eq. 4)
t
2
+ t
INT
x(1ń2)
R0x0A[3:0]orR0xD1[3:0]
(eq. 5)
t
3
+ t
INT
x(1ń2)
R0x0A[7:4]orR0xD1[7:4]
(eq. 6)
As a default for auto exposure, t
2
is 1/16 of t
INT
, t
3
is 1/64
of t
INT
.
When the auto adjust enabler is disabled (set LOW ), t
1
, t
2
,
and t
3
may be programmed through the two−wire serial
interface:
t
1
+ Coarse SW1(row * times) ) Fine SW1(pixel * times)
(eq. 7)
t
2
+ Coarse SW2 * Coarse SW1 ) Fine SW2 * Fine SW1
(eq. 8)
t
3
+ Total Integration * t
1
* t
2
+ Coarse Total Shutter Width ) Fine Shutter Width Totall * t
1
* t
2
(eq. 9)
For context A these become:
t
1
+ R0x08 ) R0xD3
(eq. 10)
t
3
+ R0x09 * R0x08 ) R0xD4 * R0xD3
(eq. 11)
t
3
+ R0x0B ) R0xD4 * t
1
* t
2
(eq. 12)
For context B these are:
t
1
+ R0xCF ) R0xD6
(eq. 13)
t
3
+ R0xD0 * R0xCF ) R0xD7 * R0xD6
(eq. 14)
t
3
+ R0xD2 ) R0xD8 * t
1
* t
2
(eq. 15)
MT9V024/D
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20
In all cases above, the coarse component of total
integration time may be based on the result of AEC or values
in R0x0B and R0xD2, depending on the settings.
Similar to Fine Shutter Width Total registers, the user
must not set the Fine Shutter Width 1 or Fine Shutter Width
2 register to exceed the row time (Horizontal Blanking +
Window Width). The absolute maximum value for the Fine
Shutter Width registers is 1774 master clocks.
ADC Companding Mode
By default, ADC resolution of the sensor is 10−bit.
Additionally, a companding scheme of 12−bit into 10−bit is
enabled by the ADC Companding Mode register. This mode
allows higher ADC resolution, which means less
quantization noise at low light, and lower resolution at high
light, where good ADC quantization is not so critical
because of the high level of the photon’s shot noise.
256
512
1,024 2,048 4,096
256
512
1,024
768
10−bit
Codes
12−bit
Codes
No companding (0 −255 0 −255)
256 −383)2 to 1 Companding (256− 511
4 to 1 Companding (512− 2047 384 − 767)
768 − 1023)8 to 1 Companding (2,048 − 4095
Figure 25. 12− to 10−Bit Companding Chart
GAIN SETTINGS
Changes to Gain Settings
When the analog gain (R0x35 for context A or R0x36 for
context B) or the digital gain settings (R0x80
–R0x98) are
changed, the gain is updated on the next frame start. The gain
setting must be written before the frame boundary to take
effect the next frame. The frame boundary is slightly after
the falling edge of Frame_Valid. In Figure 26 this is shown
by the dashed vertical line labeled Frame Start.
Both analog and digital gain change regardless of whether
the integration time is also changed simultaneously. Digital
gain will change as soon as the register is written. Additional
details on this latency can be found in AND9251/D Latency
of Exposure or Gain Switch.
frame n+1 frame n+2
frame n
write new gain value (Gain “B”)
idleidle
Readout Gain “B”Readout Gain “B”
Readout Gain “B”
Readout Gain “B”
Readout Gain “A”
New image available
at output
Frame−start writes new
gain value (Exp “B”)
AGC −sample acti-
vates new gain
value (Gain “B”)
AEC −sample point
Figure 26. Latency of Gain Register(s) in Master Mode
Readout Gain “A”
Frame−start
MT9V024/D
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21
Analog Gain
Analog gain is controlled by:
• R0x35 Global Gain context A
• R0x36 Global Gain context B
The formula for gain setting is:
Gain + Bits[6 : 0] x 0.0625
(eq. 16)
The analog gain range supported in the MT9V024 is
1X
–4X with a step size of 6.25 percent. To control gain
manually with this register, the sensor must NOT be in AGC
mode. When adjusting the luminosity of an image, it is
recommended to alter exposure first and yield to gain
increases only when the exposure value has reached
a maximum limit.
Analog gain = bits (6:0) x 0.0625 for values 16–31
Analog gain = bits (6:0)/2 x 0.125 for values 32–64
For values 16–31: each LSB increases analog gain
0.0625v/v. A value of 16 = 1X gain.
Range: 1X to 1.9375X.
For values 32–64: each 2 LSB increases analog gain
0.125v/v (that is, double the gain increase for 2 LSB).
Range: 2X to 4X. Odd values do not result in gain increases;
the gain increases by 0.125 for values 32, 34, 36, and so on.
Digital Gain
Digital gain is controlled by:
• R0x99−R0xA4 Tile Coordinates
• R0x80−R0x98 Tiled Digital Gain and Weight
In the MT9V024, the gain logic divides the image into 25
tiles, as shown in Figure 27. The size and gain of each tile can
be adjusted using the above digital gain control registers.
Separate tile gains can be assigned for context A and context
B.
Registers 0x99–0x9E and 0x9F–0xA4 represent the
coordinates X0/5–X5/5 and Y0/5–Y5/5 in Figure 27 on page
31, respectively.
Digital gains of registers 0x80–0x98 apply to their
corresponding tiles. The MT9V024 supports a digital gain
of 0.25–3.75X.
When binning is enabled, the tile offsets maintain their
absolute values; that is, tile coordinates do not scale with row
or column bin setting. Digital gain is applied as soon as
register is written.
NOTE: There is one exception, for the condition when
Column Bin 4 is enabled (R0x0D[3:2] or
R0x0E[3:2] = 2). For this case, the value for
Digital Tile Coordinate X–direction must be
doubled.
The formula for digital gain setting is:
Digital Gain + Bits[3 : 0] x 0.25
(eq. 17)
X
0/5
X
1/5
X
2/5
X
3/5
X
4/5
X
5/5
Y
0/5
Y
2/5
Y
1/5
Y
3/5
Y
4/5
Y
5/5
Figure 27. Tiled Sample
x0_y0 x1_y0
x4_y0
x0_y1 x1_y1
x4_y1
x0_y2 x1_y2
x4_y2
x0_y3 x1_y3
x4_y3
x0_y4 x1_y4
x4_y4
Black Level Calibration
Black level calibration is controlled by:
• Frame Dark Average: R0x42
• Dark Average Thresholds: R0x46
• Black Level Calibration Control: R0x47
• Black Level Calibration Value: R0x48
• Black Level Calibration Value Step Size: R0x4C
The MT9V024 has automatic black level calibration
on−chip, and if enabled, its result may be used in the offset
correction shown in Figure 28.
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MT9V024IA7XTM-DP2

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Buy MT9V024IA7XTM-DP2
Manufacturer:
ON Semiconductor
Description:
Image Sensors VGA 1/3 GS CIS Image Sensor
Lifecycle:
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