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MT9V024IA7XTM-DP2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40
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Table 10. LVDS PACKET FORMAT IN STAND−ALONE MODE (Stereoscopy Mode Bit De−Asserted)
12 Bit Packet
Use_10−bit_pixels Bit De−Asserted
(8−Bit Mode)
Use_10−bit_pixels Bit Asserted
(10−Bit Mode)
Bit [0] 1’b1(Start bit) 1’b1(Start bit)
Bit [1] Pixel Data [2] Pixel Data [0]
Bit [2] Pixel Data [3] Pixel Data [1]
Bit [3] Pixel Data [4] Pixel Data [2]
Bit [4] Pixel Data [5] Pixel Data [3]
Bit [5] Pixel Data [6] Pixel Data [4]
Bit [6] Pixel Data [7] Pixel Data [5]
Bit [7] Pixel Data [8] Pixel Data [6]
Bit [8] Pixel Data [9] Pixel Data [7]
Bit [9] Line_Valid Pixel Data [8]
Bit [10] Frame_Valid Pixel Data [9]
Bit [11] 1’b0(Stop bit) 1’b0(Stop bit)
5. In stereoscopic mode, the packet size is 18 bits (2 frame bits and 16 payload bits). The packet consists of a start bit, the master pixel byte
(with sync codes), the slave byte (with sync codes), and the stop bit.)
Table 11. LVDS PACKET FORMAT IN STEREOSCOPY MODE (Stereoscopy Mode Bit Asserted)
18−bit Packet
Function
Bit [0] 1’b1 (Start bit)
Bit [1] Master Sensor Pixel Data [2]
Bit [2] Master Sensor Pixel Data [3]
Bit [3] Master Sensor Pixel Data [4]
Bit [4] Master Sensor Pixel Data [5]
Bit [5] Master Sensor Pixel Data [6]
Bit [6] Master Sensor Pixel Data [7]
Bit [7] Master Sensor Pixel Data [8]
Bit [8] Master Sensor Pixel Data [9]
Bit [9] Slave Sensor Pixel Data [2]
Bit [10] Slave Sensor Pixel Data [3]
Bit [11] Slave Sensor Pixel Data [4]
Bit [12] Slave Sensor Pixel Data [5]
Bit [13] Slave Sensor Pixel Data [6]
Bit [14] Slave Sensor Pixel Data [7]
Bit [15] Slave Sensor Pixel Data [8]
Bit [16] Slave Sensor Pixel Data [9]
Bit [17] 1’b0 (Stop bit)
Control signals LV and FV can be reconstructed from their
respective preceding and succeeding flags that are always
embedded within the pixel data in the form of reserved
words.
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Table 12. RESERVED WORDS IN THE PIXEL DATA STREAM
Pixel Data Reserved Word Flag
0 Precedes frame valid assertion
1 Precedes line valid assertion
2 Succeeds line valid de−assertion
3 Succeeds frame valid de−assertion
When LVDS mode is enabled along with column binning
(bin 2 or bin 4, R0x0D[3:2]), the packet size remains the
same but the serial pixel data stream repeats itself depending
on whether 2X or 4X binning is set:
• For bin 2, LVDS outputs double the expected data
(pixel 0,0 is output twice in sequence, followed by pixel
0, 1 twice, …).
• For bin 4, LVDS outputs 4 times the expected data
(pixel 0,0 is output 4 times in sequence followed by
pixel 0, 1 times 4, …).
The receiving hardware will need to undersample the
output stream,getting data either every 2 clocks (bin 2) or
every 4 (bin 4) clocks.
If the sensor provides a pixel whose value is 0, 1, 2, or 3
(that is, the same as a reserved word) then the outgoing serial
pixel value is switched to 4.
LVDS Enable and Disable
The Table 10 and Table 11 further explain the state of the
LVDS output pins depending on LVDS control settings.
When the LVDS block is not used, it may be left powered
down to reduce power consumption.
Table 13. SER_DATAOUT_*STATE
R0xB1[1]
LVDS power down
R0xB3[4]
LVDS data power down
SER_DATAOUT_*
0 0 Active
0 1 Active
1 0 Z
1 1 Z
Table 14. SER_DATAOUT_*STATE
R0xB1[1]
LVDS power down
R0xB2[4]
LVDS shift−clk power down
SHFT_CLKOUT_*
0 0 Active
0 1 Z
1 0 Z
1 1 Z
6. ERROR pin: When the sensor is not in stereo mode, the ERROR pin is at LOW.
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LVDS Data Bus Timing
The LVDS bus timing waveforms and timing
specifications are shown in Table 12 and Figure 37.
Figure 37. LVDS Timing
Data Rise/Fall Time
(10% − 90%)
Data Setup Time Data Hold Time
LVDS Data Output
(SER_DATAOUT_N/P)
LVDS Clock Output
(Shift_CLKOUT_N/P)
Clock Rise/Fall Time
(10% − 90%)
Clock Jitter
Table 15. LVDS AC TIMING SPECIFICATIONS
(VPWR = 3.3V ± 0.3V; T
J
= –40_C to +105_C; output load = 100 ; frequency 27 MHz)
Parameter
Minimum Typical Maximum Unit
LVDS clock rise time − 0.22 0.30 ns
LVDS clock fall time − 0.22 0.30 ns
LVDS data rise time − 0.28 0.30 ns
LVDS data fall time − 0.28 0.30 ns
LVDS data setup time 0.3 0.67 − ns
LVDS data hold time 0.1 1.34 − ns
LVDS clock jitter − 92 ps
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40

MT9V024IA7XTM-DP2

Mfr. #:
Buy MT9V024IA7XTM-DP2
Manufacturer:
ON Semiconductor
Description:
Image Sensors VGA 1/3 GS CIS Image Sensor
Lifecycle:
New from this manufacturer.
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