OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

MT9V024IA7XTM-DP2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40
MT9V024/D
www.onsemi.com
31
ELECTRICAL SPECIFICATIONS
Table 16. DC ELECTRICAL CHARACTERISTICS OVER TEMPERATURE
(V
PWR
= 3.3V ± 0.3 V; T
J
= −40°C to + 105°C; Output Load = 10pF; Frequency 13 MHz to 27 MHz; LVDS off)
Symbol
Definition Condition Min Typ Max Unit
VIH Input HIGH Voltage VPWR − 1.4 − V
VIL Input LOW Voltage − 1.3 V
IIN Input Leakage Current No pull−up resistor; VIN = VPWR or VGND −5 – 5
A
VOH Output HIGH Voltage
IOH = –4.0 mA
VPWR − 0.3 – – V
VOL Output LOW Voltage
IOL = 4.0 mA
– –
0.3
V
IOH Output HIGH Current
VOH = VDD - 0.7
−11 – – mA
IOL Output LOW Current VOL = 0.7 – – 11 mA
IPWRA Analog Supply Current Default settings – 12 20 mA
IPIX Pixel Supply Current Default settings – 1.1 3 mA
IPWRD Digital Supply Current
Default settings, CLOAD = 10 pF
– 42 60 mA
ILVDS LVDS Supply Current Default settings with LVDS on – 13 16 mA
IPWRA
Standby
Analog Standby Supply Current STDBY = VDD − 0.2 3
A
IPWRD
Standby
Clock Off
Digital Standby Supply Current with
Clock off
STDBY = VDD, CLKIN = 0 MHz
− 0.1 10
A
IPWRD
Standby
Clock On
Digital Standby Supply Current with
Clock on
STDBY= VDD, CLKIN = 27 MHz
− 1 2 mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 17. DC ELECTRICAL CHARACTERISTICS (V
PWR
= 3.3 V ± 0.3 V; T
A
= Ambient = 25 °C)
Symbol Definition Condition Min Typ Max Unit
LVDS DRIVER DC SPECIFICATIONS
|V
OD| Output Differential Voltage
R
LOAD
= 100 ±1%
250 – 400 mV
|DVOD| Change in VOD Between Complementary Output States − − 50 mV
VOS Output Offset Voltage 1.0 1.2 1.4 V
DVOS Pixel Array Current − − 35 mV
IOS Digital Supply Current ±10 mA
IOZ Output Current When Driver is Tristate ±1
A
LVDS RECEIVER DC SPECIFICATIONS
V
IDTH+ Input Differential
| VGPD| < 925 mV
–100 – 100 mV
Iin Input Current – –
±20
A
MT9V024/D
www.onsemi.com
32
Table 18. ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Minimum Maximum Unit
VSUPPLY Power supply voltage (all supplies) –0.3 4.5 V
ISUPPLY Total power supply current – 200 mA
IGND Total ground current –
200
mA
VIN DC input voltage –0.3
VDD + 0.3
V
VOUT DC output voltage –0.3
VDD + 0.3
V
TSTG (Note 7)
Storage temperature –50 +150 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
7. This is a stress rating only, and functional operation of the device at these other conditions above those indicated in the operational sections
of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table 19. AC ELECTRICAL CHARACTERISTICS (V
PWR
= 3.3 V ± 0.3 V; T
J
= −40°C to + 105°C; Output Load = 10pF)
Symbol Definition Condition Minimum Typical Maximum Unit
SYSCLK Input Clock Frequency 13.0 26.6 27.0 MHz
Clock Duty Cycle 45.0
50.0
55.0 %
t
R
Input Clock Rise Time – 3 5 ns
t
F
Input Clock Fall Time – 3 5 ns
t
PLH
P
SYSCLK to PIXCLK Propagation Delay CLOAD = 10 pF 4 6 8 ns
t
PD
PIXCLK to Valid DOUT(9:0) Propagation Delay CLOAD = 10 pF –3 0.6 3 ns
t
SD
Data Setup Time 14 16 – ns
t
HD
Data Hold Time 14 16 –
t
PFLR
PIXCLK to LV Propagation Delay CLOAD = 10 pF 5 7 9 ns
t
PFLF
PIXCLK to FV Propagation Delay CLOAD = 10 pF 5 7 9 ns
Propagation Delays for PIXCLK and Data Out Signals
The pixel clock is inverted and delayed relative to the
master clock. The relative delay from the master clock
(SYSCLK) rising edge to both the pixel clock (PIXCLK)
falling edge and the data output transition is typically 7 ns.
Note that the falling edge of the pixel clock occurs at
approximately the same time as the data output transitions.
See Table 16 for data setup and hold times.
Figure 38. Propagation Delays for PIXCLK and Data Out Signals
t
t
R
t
F
D
OUT
(9:0)
t
PLH
P
SYSCLK
PIXCLK
t
HDSD
t
PDPD
D
OUT(9:0)
MT9V024/D
www.onsemi.com
33
Propagation Delays for FRAME_VALID and
LINE_VALID Signals
The LV and FV signals change on the same rising master
clock edge as the data output. The LV goes HIGH on the
same rising master clock edge as the output of the first valid
pixel’s data and returns LOW on the same master clock
rising edge as the end of the output of the last valid pixel’s
data.
As shown in the “Output Data Timing”, FV goes HIGH
143 pixel clocks before the first LV goes HIGH. It returns
LOW 23 pixel clocks after the last LV goes LOW.
Figure 39. Propagation Delays for FRAME_VALID and LINE_VALID Signals
FRAME_VALID
LINE_VALID
FRAME_VALID
LINE_VALID
t
PIXCLK PIXCLK
P
t
FLR FLF
PP
P
P
Two-Wire Serial Bus Timing
Detailed timing waveforms and parameters for the
two−wire serial interface bus are shown in Figure 40 and
Table 17.
Figure 40. Two−Wire Bus Timing Parameters
S
DATA
S
CLK
t
f
t
LOW
T
HD;STA
S
t
r
t
HD;DAT
t
HIGH
T
SU;DAT
t
f
T
SU;STA
Sr
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40

MT9V024IA7XTM-DP2

Mfr. #:
Buy MT9V024IA7XTM-DP2
Manufacturer:
ON Semiconductor
Description:
Image Sensors VGA 1/3 GS CIS Image Sensor
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet