UJA1066_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 17 March 2010 3 of 70
NXP Semiconductors
UJA1066
High-speed CAN fail-safe system basis chip
2.3 Power management
Smart operating modes and power management modes
Cyclic wake-up capability in Standby and Sleep modes
Local wake-up input with cyclic supply feature
Remote wake-up capability via the CAN-bus
External voltage regulators can easily be incorporated into the power supply system
(flexible and fail-safe)
42 V battery-related high-side switch for driving external loads such as relays and
wake-up switches
Intelligent maskable interrupt output
2.4 Fail-safe features
Safe and predictable behavior under all conditions
Programmable fail-safe coded window and time-out watchdog with on-chip oscillator,
guaranteeing autonomous fail-safe system supervision
Fail-safe coded 16-bit SPI interface for the microcontroller
Global enable pin for the control of safety-critical hardware
Detection and detailed reporting of failures:
On-chip oscillator failure and watchdog alerts
Battery and voltage regulator undervoltages
CAN-bus failures (short circuits and open-circuit bus wires)
TXD and RXD clamping situations and short circuits
Clamped or open reset line
SPI message errors
Overtemperature warning
ECU ground shift (two selectable thresholds)
Rigorous error handling based on diagnostics
Supply failure early warning allows critical data to be stored
23 bits of access-protected RAM available (e.g. for logging cyclic problems)
Reporting in a single SPI message; no assembly of multiple SPI frames needed
Limp-home output signal for activating application hardware in case system enters
Fail-safe mode (e.g. for switching on warning lights)
Fail-safe coded activation of Software development mode and Flash mode
Unique SPI readable device type identification
Software-initiated system reset
