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UJA1066TW/5V0/T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P70
UJA1066_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 17 March 2010 10 of 70
NXP Semiconductors
UJA1066
High-speed CAN fail-safe system basis chip
Entering Normal mode does not activate the CAN transceiver automatically. The CAN
Mode Control (CMC) bit must be set to activate the CAN medium if required, allowing
local cyclic wake-up scenarios to be implemented without affecting the CAN-bus.
6.2.5 Standby mode
In Standby mode, the system is in a reduced current consumption state. Entering Standby
mode overrides the CMC bit, allowing the CAN transceiver to enter the low-power mode
autonomously. The watchdog will, however, continue to monitor the microcontroller
(Time-out mode) since it is powered via pin V1.
If the host microcontroller supports a low-power Standby or Stop mode with reduced
current consumption, the watchdog can be switched off entirely when the SBS is in
Standby mode. The SBC will monitor the microcontroller supply current to ensure that no
unobserved phases occur while the watchdog is disabled and the microcontroller is
running. The watchdog will remain active until the supply current drops below I
thL(V1)
,
when it will be disabled.
Should the current increase to I
thH(V1)
(e.g. as result of a microcontroller wake-up from
application specific hardware) the watchdog will start operating again with the previously
used time-out period. If the watchdog is not triggered correctly, a system reset will occur
and the SBC will enter Start-up mode.
If Standby mode is entered from Normal mode with the selected watchdog OFF option,
the watchdog will use the maximum time-out as defined for Standby mode until the supply
current drops below the current detection threshold; the watchdog is now OFF. If the
current increases again, the watchdog will be activated immediately, again using the
maximum watchdog time-out period. If the watchdog OFF option is selected during
Standby mode, the watchdog period last used will define the time for the supply current to
fall below the current detection threshold. This allows the user to align the current
supervisor function with the requirements of the application.
Generally, the microcontroller can be activated from Standby mode via a system reset or
via an interrupt without reset. This allows for the implementation of differentiated start-up
behavior from Standby mode, depending on the needs of the application:
• If the watchdog is still running during Standby mode, it can be used for cyclic wake-up
behavior of the system. A dedicated Watchdog Time-out Interrupt Enable (WTIE) bit
allows the microcontroller to decide whether to receive an interrupt or a hardware
reset upon overflow. The interrupt option will be cleared in hardware automatically
with each watchdog overflow to ensure that a failing main routine is detected while the
interrupt service is still operating. So the application software must set the interrupt
behavior before each standby cycle begins.
• Any wake-up via the CAN-bus together with a local wake-up event will force a system
reset event or generate an interrupt to the microcontroller. So it is possible to exit
Standby mode without performing a system reset if necessary.
When an interrupt event occurs, the application software has to read the Interrupt register
within t
RSTN(INT)
. Otherwise a fail-safe system reset is forced and Start-up mode will be
entered. If the application has read out the Interrupt register within the specified time, it
can decide whether to switch to Normal mode via an SPI access or to remain in Standby
mode.
The following operations are possible from Standby mode:
UJA1066_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 17 March 2010 11 of 70
NXP Semiconductors
UJA1066
High-speed CAN fail-safe system basis chip
• Cyclic wake-up by the watchdog via an interrupt signal to the microcontroller (the
microcontroller is triggered periodically and checked for the correct response)
• Cyclic wake-up by the watchdog via a reset signal (a reset is performed periodically;
the SBC provides information about the reset source to allow different start
sequences after reset)
• Wake-up by activity on the CAN-bus via an interrupt signal to the microcontroller
• Wake-up by bus activity on the CAN-bus via a reset signal
• Wake-up by increasing the microcontroller supply current without a reset signal
(where a stable supply is needed for the microcontroller RAM contents to remain valid
and wake-up from an external application not connected to the SBC)
• Wake-up by increasing the microcontroller supply current with a reset signal
• Wake-up due to a falling edge at pin WAKE forcing an interrupt to the microcontroller
• Wake-up due to a falling edge at pin WAKE forcing a reset signal
6.2.6 Sleep mode
In Sleep mode the microcontroller power supply (V1) and the INH/LIMP-controlled
external supplies are switched off entirely, resulting in minimum system power
consumption. In this mode, the watchdog runs in Time-out mode or is completely off.
Entering Sleep mode results in an immediate LOW level on pin RSTN, stopping all
microcontroller operations. The INH/LIMP output is floating in parallel and pin V1 is
disabled. Only pin SYSINH can remain active to support the V2 voltage supply (if bit V2C
is set; see Table 12
). V3 can also be ON, OFF or in Cyclic mode to supply external
wake-up switches.
If the watchdog is not disabled by software, it will continue to run and will force a system
reset once the programmed watchdog period has expired. The SBC then enters Start-up
mode and pin V1 becomes active again. This behavior can be used to implement cyclic
wake-up from Sleep mode.
Depending on the application, the following operations can be selected from Sleep mode:
• Cyclic wake-up by the watchdog (only in Time-out mode); a reset is performed
periodically, the SBC provides information about the reset source to allow the
microcontroller to choose between different start up sequences after reset
• Wake-up by activity on the CAN-bus or falling edge on pin WAKE
• An overload on V3, only if V3 is in a cyclic or a continuously ON mode
6.2.7 Flash mode
Flash mode can only be entered from Normal mode by entering a specific Flash mode
entry sequence. This fail-safe control sequence comprises three consecutive write
accesses to the Mode register, within the legal windows of the watchdog, using the
operating mode codes 111, 001 and 111 respectively. Once this sequence has been
received, the SBC will enter Start-up mode and perform a system reset using the related
reset source information (bits RSS[3:0] = 0110).
UJA1066_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 17 March 2010 12 of 70
NXP Semiconductors
UJA1066
High-speed CAN fail-safe system basis chip
Once in Start-up mode the application software has to write Operating Mode code 011 to
the Mode register within t
WD(init)
to initiate a transition to Flash mode. This causes a
successfully received hardware reset (handshake between the SBC and the
microcontroller) to be fed back. The transition from Start-up mode to Flash mode can only
occur once after the Flash entry sequence has been completed.
The application can choose not to enter Flash mode but instead return to Normal mode by
using the Operating Mode code 101 for handshaking. This erases the Flash mode entry
sequence.
The watchdog behavior in Flash mode is similar to its time-out behavior in Standby mode,
but Operating Mode code 111 must be used for serving the watchdog. If this code is not
used or if the watchdog overflows, the SBC will immediately force a reset and a transition
to Start-up mode. Operating Mode code 110 (leave Flash mode) is used to correctly exit
Flash mode. This results in a system reset with the corresponding reset source
information. Other Mode register codes will cause a forced reset with reset source code
‘illegal Mode register code’.
6.3 On-chip oscillator
The on-chip oscillator provides the clock signal for all digital functions and is the timing
reference for the on-chip watchdog and the internal timers.
If the on-chip oscillator frequency is too low or the oscillator is not running at all, there is
an immediate transition to Fail-safe mode. The SBC will stay in Fail-safe mode until the
oscillator has recovered to its normal frequency and the system receives a wake-up
event.
6.4 Watchdog
The watchdog provides the following timing functions:
• Start-up mode; needed to give the software the opportunity to initialize the system
• Window mode; detects ‘too early’ and ‘too late’ accesses in Normal mode
• Time-out mode; detects a ‘too late’ access, can also be used to restart or interrupt the
microcontroller from time to time (cyclic wake-up function)
• OFF mode; fail-safe shutdown during operation prevents any blind spots occurring in
the system supervision
The watchdog is clocked directly by the on-chip oscillator.
To guarantee fail-safe control of the watchdog via the SPI, all watchdog accesses are
coded with redundant bits. Therefore, only certain codes are allowed for a proper
watchdog service.
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UJA1066TW/5V0/T

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Buy UJA1066TW/5V0/T
Manufacturer:
NXP Semiconductors
Description:
CAN Interface IC IC CAN/LIN FAIL-SAFE HS 32
Lifecycle:
New from this manufacturer.
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