UJA1066_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 17 March 2010 58 of 70
NXP Semiconductors
UJA1066
High-speed CAN fail-safe system basis chip
10. Dynamic characteristics
Table 27. Dynamic characteristics
T
vj
=
−
40
°
C to +150
°
C; V
BAT42
=5.5V to52V; V
BAT14
=5.5V to27V; V
BAT42
≥
V
BAT14
−
1 V; unless otherwise specified. All
voltages are defined with respect to ground. Positive currents flow into the IC.
[1]
Symbol Parameter Conditions Min Typ Max Unit
Serial peripheral interface timing; pins SCS, SCK, SDI and SDO (see Figure 21
)
[2]
T
cyc
clock cycle time 960 - - ns
t
lead
enable lead time clock is LOW when SPI select
falls
240 - - ns
t
lag
enable lag time clock is LOW when SPI select
rises
240 - - ns
t
SCKH
clock HIGH time 480 - - ns
t
SCKL
clock LOW time 480 - - ns
t
su
input data setup time 80 - - ns
t
h
input data hold time 400 - - ns
t
DOV
output data valid time pin SDO; C
L
= 10 pF - - 400 ns
t
SSH
SPI select HIGH time 480 - - ns
CAN transceiver timing; pins CANL, CANH, TXDC and RXDC
t
t(reces-dom)
output transition time
recessive to dominant
10 % to 90 %; C = 100 pF;
R=60Ω; see Figure 22
and
Figure 23
-100-ns
t
t(dom-reces)
output transition time
dominant to recessive
90 % to 10 %; C = 100 pF;
R=60Ω; see Figure 22
and
Figure 23
-100-ns
t
PHL
propagation delay TXDC to
RXDC (HIGH-to-LOW
transition)
50 % V
TXDC
to 50 % V
RXDC
;
C=100pF; R=60Ω; see
Figure 22
and Figure 23
70 120 220 ns
t
PLH
propagation delay TXDC to
RXDC (LOW-to-HIGH
transition)
50 % V
TXDC
to 50 % V
RXDC
;
C=100pF; R=60Ω; see
Figure 22
and Figure 23
70 120 220 ns
t
TXDC(dom)
TXDC permanent dominant
disable time
Active mode, On-line mode or
On-line Listen mode;
V
V2
=5V; V
TXDC
=0V
1.5 - 6 ms
t
CANH(dom1)
,
t
CANL(dom1)
minimum dominant time first
pulse for wake-up on pins
CANH and CANL
Off-line mode 3 - - μs
t
CANH(reces)
,
t
CANL(reces)
minimum recessive time
pulse (after first dominant)
for wake-up on pins CANH
and CANL
Off-line mode 1 - - μs
t
CANH(dom2)
,
t
CANL(dom2)
minimum dominant time
second pulse for wake-up on
pins CANH, CANL
Off-line mode 1 - - μs
t
timeout
time-out period between
wake-up message and
confirm message
On-line Listen mode 115 - 285 ms
