UJA1066_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 17 March 2010 41 of 70
NXP Semiconductors
UJA1066
High-speed CAN fail-safe system basis chip
6.13 Test modes
6.13.1 Software development mode
The Software development mode is intended to support software developers in writing
and pretesting application software without having to work around watchdog triggering
and without unwanted jumps to Fail-safe mode.
In Software development mode, the following events do not force a system reset:
• Watchdog overflow in Normal mode
• Watchdog window miss
• Interrupt time-out
• Elapsed start-up time
However, in the case of a watchdog trigger failure the reset source information is still
written to the System Status register, as if a real reset event had occurred.
The exclusion of watchdog related resets allows for simplified software testing because
problems with watchdog triggering can be indicated by interrupts instead of resets. The
SDM bit does not affect the watchdog behavior in Standby and Sleep modes. This allows
the cyclic wake-up behavior to be evaluated in these modes.
All transitions to Fail-safe mode are disabled. This makes it possible to work with an
external emulator that clamps the reset line LOW in debugging mode. A V1 undervoltage
of more than t
V1(CLT)
is the only exception that results in a transition to Fail-safe mode (to
protect the SBC). Transitions from Start-up mode to Restart mode are still possible.
There are two ways to enter Software development mode. One is by setting the ISDM bit
in the Special Mode register (Table 13
); possible only after the initial connection of a
battery while the SBC is in Start-up mode. The other is by applying the correct V
th(TEST)
input voltage at pin TEST before the battery has been connected to pin BAT42.
Table 22. Special Mode register: status at reset
Symbol Name Power-on Start-up Restart
ISDM initialize software development mode 0 (no) no change no change
ERREM error pin emulation mode 0 (EN function) no change no change
WDPRE watchdog prescale factor 00 (factor 1) no change no change
V1RTHC V1 reset threshold control 00 (90 %) no change 00 (90 %)
Table 23. General Purpose register 0 and General Purpose Feedback register 0: status at reset
Symbol Name Power-on Start-up Restart
DIC device identification control 0 (device ID) no change no change
GP0[10:7] general purpose bits 10 to 7 (version) mask version no change no change
GP0[6:0] general purpose bits 6 to 0 (SBC type) 000 0110 (UJA1066) no change no change
Table 24. General Purpose register 1 and General Purpose Feedback register 1: status at reset
Symbol Name Power-on Start-up Restart
GP1[11:0] general purpose bits 11 to 0 0000 0000 0000 no change no change
