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UJA1066TW/5V0/T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P70
UJA1066_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 17 March 2010 28 of 70
NXP Semiconductors
UJA1066
High-speed CAN fail-safe system basis chip
Table 6. Mode register bit description (bits 11 to 6)
[1]
Bit Symbol Description Value Time
Normal
mode (ms)
Standby
mode (ms)
Flash mode
(ms)
Sleep mode
(ms)
11 to 6 NWP[5:0] Nominal
Watchdog Period
WDPRE = 00 (as
set in the Special
Mode register)
00 1001 4 20 20 160
00 1100 8 40 40 320
01 0010 16 80 80 640
01 0100 32 160 160 1024
01 1011 40 320 320 2048
10 0100 48 640 640 3072
10 1101 56 1024 1024 4096
11 0011 64 2048 2048 6144
11 0101 72 4096 4096 8192
11 0110 80 OFF
[2]
8192 OFF
[3]
Nominal
Watchdog Period
WDPRE = 01 (as
set in the Special
Mode register)
00 1001 6 30 30 240
00 1100 12 60 60 480
01 0010 24 120 120 960
01 0100 48 240 240 1536
01 1011 60 480 480 3072
10 0100 72 960 960 4608
10 1101 84 1536 1536 6144
11 0011 96 3072 3072 9216
11 0101 108 6144 6144 12288
11 0110 120 OFF
[2]
12288 OFF
[3]
Nominal
Watchdog Period
WDPRE = 10 (as
set in the Special
Mode register)
00 1001 10 50 50 400
00 1100 20 100 100 800
01 0010 40 200 200 1600
01 0100 80 400 400 2560
01 1011 100 800 800 5120
10 0100 120 1600 1600 7680
10 1101 140 2560 2560 10240
11 0011 160 5120 5120 15360
11 0101 180 10240 10240 20480
11 0110 200 OFF
[2]
20480 OFF
[3]
UJA1066_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 17 March 2010 29 of 70
NXP Semiconductors
UJA1066
High-speed CAN fail-safe system basis chip
[1] The nominal watchdog periods are directly related to the SBC internal oscillator. The given values are valid for f
osc
= 512 kHz.
[2] See Section 6.4.4
.
[3] The watchdog is immediately disabled on entering Sleep mode, with watchdog OFF behavior selected, because pin RSTN is
immediately pulled LOW by the mode change. V1 is switched off after pulling pin RSTN LOW to guarantee a safe Sleep mode entry
without dips on V1. See Section 6.4.4
.
6.12.4 System Status register
This register allows status information to be read back from the SBC. This register can be
read in all modes.
11 to 6 NWP[5:0] Nominal
Watchdog Period
WDPRE = 11 (as
set in the Special
Mode register)
00 1001 14 70 70 560
00 1100 28 140 140 1120
01 0010 56 280 280 2240
01 0100 112 560 560 3584
01 1011 140 1120 1120 7168
10 0100 168 2240 2240 10752
10 1101 196 3584 3584 14336
11 0011 224 7168 7168 21504
11 0101 252 14336 14336 28672
11 0110 280 OFF
[2]
28672 OFF
[3]
Table 6. Mode register bit description (bits 11 to 6)
[1]
…continued
Bit Symbol Description Value Time
Normal
mode (ms)
Standby
mode (ms)
Flash mode
(ms)
Sleep mode
(ms)
Table 7. System Status register bit description
Bit Symbol Description Value Function
15 and 14 A1, A0 register address 00 read System Status register
13 RRS Read Register Select 0
12 RO Read Only 1 read System Status register without writing to Mode
register
0 read System Status register and write to Mode register
UJA1066_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 17 March 2010 30 of 70
NXP Semiconductors
UJA1066
High-speed CAN fail-safe system basis chip
[1] The RSS bits are updated with each reset event and not cleared. The last reset event is captured.
6.12.5 System Diagnosis register
This register allows diagnostic information to be read back from the SBC. This register
can be read in all modes.
11 to 8 RSS[3:0] Reset Source
[1]
0000 power-on reset; first connection of BAT42 or BAT42 below
power-on voltage threshold or RSTN was forced LOW
externally
0001 cyclic wake-up out of Sleep mode
0010 low V1 supply; V1 has dropped below the selected reset
threshold
0011 V1 current above threshold within Standby mode while
watchdog OFF behavior and reset option (V1CMC bit) are
selected
0100 V3 voltage is down due to overload occurring during Sleep
mode
0101 SBC successfully left Flash mode
0110 SBC ready to enter Flash mode
0111 CAN wake-up event
1000 reserved for SBCs with LIN transceiver
1001 local wake-up event (via pin WAKE)
1010 wake-up out of Fail-safe mode
1011 watchdog overflow
1100 watchdog not initialized in time; t
WD(init)
exceeded
1101 watchdog triggered too early; window missed
1110 illegal SPI access
1111 interrupt not served within t
RSTN(INT)
7 CWS CAN Wake-up Status 1 CAN wake-up detected; cleared upon read
0 no CAN wake-up
6 - reserved 0 reserved for SBCs with LIN transceiver
5 EWS Edge Wake-up Status 1 pin WAKE negative edge detected; cleared upon read
0 pin WAKE no edge detected
4 WLS WAKE Level Status 1 pin WAKE above threshold
0 pin WAKE below threshold
3 TWS Temperature Warning
Status
1 chip temperature exceeds the warning limit
0 chip temperature is below the warning limit
2 SDMS Software Development
Mode Status
1 Software Development mode on
0 Software Development mode off
1 ENS Enable Status 1 pin EN output activated (V1-related HIGH level)
0 pin EN output released (LOW level)
0 PWONS Power-on reset Status 1 power-on reset; cleared after a successfully entered
Normal mode
0 no power-on reset
Table 7. System Status register bit description
…continued
Bit Symbol Description Value Function
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P70

UJA1066TW/5V0/T

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Buy UJA1066TW/5V0/T
Manufacturer:
NXP Semiconductors
Description:
CAN Interface IC IC CAN/LIN FAIL-SAFE HS 32
Lifecycle:
New from this manufacturer.
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