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UJA1066TW/5V0/T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P70
UJA1066_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 17 March 2010 49 of 70
NXP Semiconductors
UJA1066
High-speed CAN fail-safe system basis chip
High-speed CAN-bus lines; pins CANH and CANL
V
o(dom)
CANH dominant
output voltage
Active mode; V
TXDC
=0V;
V
V2
= 4.75 V to 5.25 V
2.85 3.6 4.25 V
CANL dominant
output voltage
Active mode; V
TXDC
=0V;
V
V2
= 4.75 V to 5.25 V
0.5 1.4 2 V
V
o(m)(dom)
matching of
dominant output
voltage
R
L
=60Ω; V
o(m)(dom)
=
V
V2
− V
CANH
− V
CANL
−0.3 - +0.3 V
V
o(dif)
differential bus
output voltage
Active mode; V
TXDC
=0V;
V
V2
= 4.75 V to 5.25 V;
R
L
=45Ω to 65 Ω
1.5 - 3 V
Active mode, On-line mode or
On-line Listen mode;
V
TXDC
=V
V1
;
V
V2
= 4.75 V to 5.25 V;
no load
−50 0 +50 mV
V
O(reces)
recessive output
voltage
Active mode, On-line mode or
On-line Listen mode;
V
TXDC
=V
V1
;
V
V2
= 4.75 V to 5.25 V;
R
L
=60Ω
2.25 2.5 2.75 V
Off-line mode; R
L
=60Ω−0.1 0 +0.1 V
V
th(dif)
differential receiver
threshold voltage
Active mode, On-line mode or
On-line Listen mode;
V
CAN
= −30 V to +30 V;
R
L
=60Ω
0.50.70.9V
Off-line mode;
V
CAN
= −30 V to +30 V;
R
L
=60Ω; measured from
recessive to dominant
0.45 0.7 1.15 V
V
th(GSD)(cm)
common-mode bus
voltage threshold
level for ground shift
detection
Active mode; GSTHC = 0;
V
V2
=5V; R
L
=60Ω;
V
cm
=0.5 × (V
CANH
+V
CANL
)
0.95 1.75 2.45 V
Active mode; GSTHC = 1;
V
V2
=5V; R
L
=60Ω;
V
cm
=0.5 × (V
CANH
+V
CANL
)
0.31 1.5V
I
o(CANH)(dom)
CANH dominant
output current
Active mode; t < t
TXDC(dom)
;
V
CANH
=0V; V
TXDC
=0V;
V
V2
=5V
−100 −75 −45 mA
I
o(CANL)(dom)
CANL dominant
output current
Active mode; t < t
TXDC(dom)
;
V
CANL
=5V; V
TXDC
=0V;
V
V2
=5V
45 75 100 mA
Table 26. Static characteristics
…continued
T
vj
=
−
40
°
C to +150
°
C, V
BAT42
= 5.5 V to 52 V; V
BAT14
= 5.5 V to 27 V; V
BAT42
≥
V
BAT14
−
1 V; unless otherwise specified. All
voltages are defined with respect to ground. Positive currents flow into the IC.
[1]
Symbol Parameter Conditions Min Typ Max Unit
UJA1066_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 17 March 2010 50 of 70
NXP Semiconductors
UJA1066
High-speed CAN fail-safe system basis chip
I
o(reces)
recessive output
current
all CAN modes; V2D = 1;
V
TXDC
=V
V1
;
V
CAN
= −40 V to +40 V
−5- +5mA
Active mode, On-line mode or
On-line Listen mode;
V2D = 0; V
TXDC
=V
V1
;
V
CAN
= −0.5 V to +5 V
−10 - +10 μA
R
i
input resistance Active mode, On-line mode or
On-line Listen mode;
V2D = 1; V
TXDC
=V
V1
;
V
CAN
= −40 V to +40 V
91528kΩ
Off-line mode;
V
CAN
= −40 V to +40 V
15 22 40 kΩ
R
i(m)
input resistance
matching
V
CANH
=V
CANL
−20 +2%
R
i(dif)
differential input
resistance
19 30 52 kΩ
C
i(cm)
common-mode input
capacitance
[3]
--20pF
C
i(dif)
differential input
capacitance
[3]
--10pF
R
sc(bus)
detectable
short-circuit
resistance between
bus lines and V
V2
,
V
BAT14
, V
BAT42
and
GND
Active mode; V
TXDC
=0V 0 - 50 Ω
CAN-bus common mode stabilization output; pin SPLIT
V
o
output voltage Active mode, On-line mode or
On-line Listen mode;
CSC=V2D=1;
⎪I
SPLIT
⎪ = 500 μA
0.3 × V
V2
0.5 × V
V2
0.7 × V
V2
V
⎪I
L
⎪ leakage current Off-line mode or CSC = 0;
V
SPLIT
= −40 V to +40 V
−10 0 +10 μA
TEST input; pin TEST
V
th(TEST)
input threshold
voltage
for entering Software
development mode;
T
j
=25°C
158V
for entering Forced normal
mode; T
j
=25°C
21013.5V
R
(pd)TEST
pull-down resistor between pin TEST and GND 2 4 8 kΩ
Table 26. Static characteristics …continued
T
vj
=
−
40
°
C to +150
°
C, V
BAT42
= 5.5 V to 52 V; V
BAT14
= 5.5 V to 27 V; V
BAT42
≥
V
BAT14
−
1 V; unless otherwise specified. All
voltages are defined with respect to ground. Positive currents flow into the IC.
[1]
Symbol Parameter Conditions Min Typ Max Unit
UJA1066_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 17 March 2010 51 of 70
NXP Semiconductors
UJA1066
High-speed CAN fail-safe system basis chip
[1] All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 °C ambient
temperature on wafer level (pretesting). Cased products are 100 % tested at 25 °C ambient temperature (final testing). Both pretesting
and final testing use correlated test conditions to cover the specified temperature and power supply voltage range.
[2] V
V1(nom)
is 3.3 V or 5 V, depending on the SBC version.
[3] Not tested in production.
[4] V2 internally supplies the SBC CAN transceiver. The supply current needed for the CAN transceiver reduces the pin V2 output
capability. The performance of the CAN transceiver can be impaired if V2 is also used to supply other circuitry while the CAN transceiver
is in use.
Temperature detection
T
j(warn)
high junction
temperature warning
level
160 175 190 °C
Table 26. Static characteristics
…continued
T
vj
=
−
40
°
C to +150
°
C, V
BAT42
= 5.5 V to 52 V; V
BAT14
= 5.5 V to 27 V; V
BAT42
≥
V
BAT14
−
1 V; unless otherwise specified. All
voltages are defined with respect to ground. Positive currents flow into the IC.
[1]
Symbol Parameter Conditions Min Typ Max Unit
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P70

UJA1066TW/5V0/T

Mfr. #:
Buy UJA1066TW/5V0/T
Manufacturer:
NXP Semiconductors
Description:
CAN Interface IC IC CAN/LIN FAIL-SAFE HS 32
Lifecycle:
New from this manufacturer.
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