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UJA1066TW/5V0/T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P70
UJA1066_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 17 March 2010 31 of 70
NXP Semiconductors
UJA1066
High-speed CAN fail-safe system basis chip
Table 8. System Diagnosis register bit description
Bit Symbol Description Value Function
15 and 14 A1, A0 register address 00 read System Diagnosis register
13 RRS Read Register Select 1
12 RO Read Only 1 read System Diagnosis register without writing to Mode
register
0 read System Diagnosis register and write to Mode register
11 GSD Ground Shift Diagnosis 1 system GND shift is outside selected threshold
0 system GND shift is within selected threshold
10 to 7 CANFD [3:0] CAN Failure Diagnosis 1111 pin TXDC is continuously clamped dominant
1110 pin RXDC is continuously clamped dominant
1100 the bus is continuously clamped dominant
1101 pin RXDC is continuously clamped recessive
1011 reserved
1010 reserved
1001 pin CANH is shorted to pin CANL
1000 pin CANL is shorted to V
CC
, V
BAT14
or V
BAT42
0111 reserved
0110 CANH is shorted to GND
0101 CANL is shorted to GND
0100 CANH is shorted to V
CC
, V
BAT14
or V
BAT42
0011 reserved
0010 reserved
0001 reserved
0000 no failure
6 and 5 - reserved 00 reserved for SBCs with LIN transceiver
4 V3D V3 Diagnosis 1 OK
0 fail; V3 is disabled due to an overload situation
3 V2D V2 Diagnosis 1 OK
[1]
0 fail; V2 is disabled due to an overload situation
2 V1D V1 Diagnosis 1 OK; V1 always above V
UV(VFI)
since last read access
0 fail; V1 was below V
UV(VFI)
since last read access; bit is set
again with read access
UJA1066_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 17 March 2010 32 of 70
NXP Semiconductors
UJA1066
High-speed CAN fail-safe system basis chip
[1] V2D will be set when V2 is reactivated after a failure. See Section 6.6.3.2.
6.12.6 Interrupt Enable register and Interrupt Enable Feedback register
These registers allow the SBC interrupt enable bits to be set, cleared and read back.
1 and 0 CANMD [1:0] CAN Mode Diagnosis 11 CAN is in Active mode
10 CAN is in On-line mode
01 CAN is in On-line Listen mode
00 CAN is in Off-line mode, or V2 is not active
Table 8. System Diagnosis register bit description
…continued
Bit Symbol Description Value Function
Table 9. Interrupt Enable and Interrupt Enable Feedback register bit description
Bit Symbol Description Value Function
15 and 14 A1, A0 register address 01 select the Interrupt Enable register
13 RRS Read Register Select 1 read the Interrupt register
0 read the Interrupt Enable Feedback register
12 RO Read Only 1 read the register selected by RRS without writing to
Interrupt Enable register
0 read the register selected by RRS and write to Interrupt
Enable register
11 WTIE Watchdog Time-out
Interrupt Enable
[1]
1 a watchdog overflow during Standby mode causes an
interrupt instead of a reset event (interrupt based cyclic
wake-up feature)
0 no interrupt forced on watchdog overflow; a reset is forced
instead
10 OTIE OverTemperature
Interrupt Enable
1 exceeding or dropping below the temperature warning limit
causes an interrupt
0 no interrupt forced
9 GSIE Ground Shift Interrupt
Enable
1 exceeding or dropping below the GND shift limit causes an
interrupt
0 no interrupt forced
8 SPIFIE SPI clock count Failure
Interrupt Enable
1 wrong number of CLK cycles (more than, or less than 16)
forces an interrupt; from Start-up mode and Restart mode a
reset is performed instead of an interrupt
0 no interrupt forced; SPI access is ignored if the number of
cycles does not equal 16
7 BATFIE BAT Failure Interrupt
Enable
1 falling edge at SENSE forces an interrupt
0 no interrupt forced
6 VFIE Voltage Failure Interrupt
Enable
1 clearing of V1D, V2D or V3D forces an interrupt
0 no interrupt forced
5 CANFIE CAN Failure Interrupt
Enable
1 any change of the CAN Failure status bits forces an
interrupt
0 no interrupt forced
4 - reserved 0 reserved for SBCs with LIN transceiver
UJA1066_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 03 — 17 March 2010 33 of 70
NXP Semiconductors
UJA1066
High-speed CAN fail-safe system basis chip
[1] This bit is cleared automatically upon each overflow event. It has to be set in software each time the interrupt behavior is required
(fail-safe behavior).
[2] WEN (in the System Configuration register) has to be set to activate the WAKE port function globally.
6.12.7 Interrupt register
The Interrupt register allows the cause of an interrupt event to be determined. The register
is cleared upon a read access and upon any reset event. Hardware ensures that no
interrupt event is lost in case there is a new interrupt forced while reading the register.
After reading the Interrupt register, pin INTN is released for t
INTN
to guarantee an edge
event at pin INTN.
The interrupts can be classified into two groups:
• Timing critical interrupts which require immediate reaction (SPI clock count failure
which needs a new SPI command to be resent immediately, and a BAT failure which
needs critical data to be saved immediately into the nonvolatile memory)
• Interrupts that do not require an immediate reaction (overtemperature, Ground Shift
and CAN failures, V1, V2 and V3 failures and the wake-ups via CAN and WAKE).
These interrupts will be signalled to the microcontroller once per watchdog period
(maximum) in Normal mode; this avoids overloading the microcontroller with
unexpected interrupt events (e.g. a chattering CAN failure). However, these interrupts
are reflected in the interrupt register
3 WIE WAKE Interrupt
Enable
[2]
1 a negative edge at pin WAKE generates an interrupt in
Normal mode, Flash mode or Standby mode
0 a negative edge at pin WAKE generates a reset in Standby
mode; no interrupt in any other mode
2 WDRIE Watchdog Restart
Interrupt Enable
1 a watchdog restart during watchdog OFF generates an
interrupt
0 no interrupt forced
1 CANIE CAN Interrupt Enable 1 CAN-bus event results in a wake-up interrupt in Standby
mode and in Normal or Flash mode (unless CAN is in
Active mode already)
0 CAN-bus event results in a reset in Standby mode; no
interrupt in any other mode
0 - reserved 0 reserved for SBCs with LIN transceiver
Table 9. Interrupt Enable and Interrupt Enable Feedback register bit description
…continued
Bit Symbol Description Value Function
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P70

UJA1066TW/5V0/T

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Buy UJA1066TW/5V0/T
Manufacturer:
NXP Semiconductors
Description:
CAN Interface IC IC CAN/LIN FAIL-SAFE HS 32
Lifecycle:
New from this manufacturer.
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