SC16IS752_SC16IS762 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 9 — 22 March 2012 10 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
7.2.2 Auto-CTS
Figure 6 shows CTS functional timing. The transmitter circuitry checks CTS before
sending the next data character. When CTS
is active, the transmitter sends the next
character. To stop the transmitter from sending the following character, CTS
must be
de-asserted before the middle of the last stop bit that is currently being sent. The
Auto-CTS
function reduces interrupts to the host system. When flow control is enabled,
CTS
level changes do not trigger host interrupts because the device automatically
controls its own transmitter. Without Auto-CTS
, the transmitter sends any data present in
the transmit FIFO and a receiver overrun error may result.
7.3 Software flow control
Software flow control is enabled through the Enhanced Features Register and the Modem
Control Register. Different combinations of software flow control can be enabled by setting
different combinations of EFR[3:0]. Table 3
shows software flow control options.
(1) When CTS is LOW, the transmitter keeps sending serial data out.
(2) When CTS
goes HIGH before the middle of the last stop bit of the current character, the transmitter finishes sending the current
character, but it does not send the next character.
(3) When CTS
goes from HIGH to LOW, the transmitter begins sending data again.
Fig 6. CTS functional timing
start bit 0 to bit 7 stopTX
CTS
002aab041
start stop
bit 0 to bit 7
Table 3. Software flow control options (EFR[3:0])
EFR[3] EFR[2] EFR[1] EFR[0] TX, RX software flow control
0 0 X X no transmit flow control
1 0 X X transmit Xon1, Xoff1
0 1 X X transmit Xon2, Xoff2
1 1 X X transmit Xon1 and Xon2, Xoff1 and Xoff2
X X 0 0 no receive flow control
X X 1 0 receiver compares Xon1, Xoff1
X X 0 1 receiver compares Xon2, Xoff2
1011transmit Xon1, Xoff1
receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0111transmit Xon2, Xoff2
receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1111transmit Xon1 and Xon2, Xoff1 and Xoff2
receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0011no transmit flow control
receiver compares Xon1 and Xon2, Xoff1 and Xoff2
SC16IS752_SC16IS762 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 9 — 22 March 2012 11 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
There are two other enhanced features relating to software flow control:
Xon Any function (MCR[5]): Receiving any character will resume operation after
recognizing the Xoff character. It is possible that an Xon1 character is recognized as
an Xon Any character, which could cause an Xon2 character to be written to the
RX FIFO.
Special character (EFR[5]): Incoming data is compared to Xoff2. Detection of the
special character sets the Xoff interrupt (IIR[4]) but does not halt transmission. The
Xoff interrupt is cleared by a read of the Interrupt Identification Register (IIR). The
special character is transferred to the RX FIFO.
7.3.1 Receive flow control
When software flow control operation is enabled, the SC16IS752/SC16IS762 will
compare incoming data with Xoff1/Xoff2 programmed characters (in certain cases, Xoff1
and Xoff2 must be received sequentially). When the correct Xoff characters are received,
transmission is halted after completing transmission of the current character. Xoff
detection also sets IIR[4] (if enabled via IER[5]) and causes IRQ
to go LOW.
To resume transmission, an Xon1/Xon2 character must be received (in certain cases
Xon1 and Xon2 must be received sequentially). When the correct Xon characters are
received, IIR[4] is cleared, and the Xoff interrupt disappears.
7.3.2 Transmit flow control
Xoff1/Xoff2 character is transmitted when the RX FIFO has passed the halt trigger level
programmed in TCR[3:0], or the selectable trigger level in FCR[7:6].
Xon1/Xon2 character is transmitted when the RX FIFO reaches the resume trigger level
programmed in TCR[7:4], or falls below the lower selectable trigger level in FCR[7:6].
The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an
ordinary character from the FIFO. This means that even if the word length is set to be 5, 6,
or 7 bits, then the 5, 6, or 7 least significant bits of Xoff1/Xoff2, Xon1/Xon2 will be
transmitted. (Note that the transmission of 5, 6, or 7 bits of a character is seldom done, but
this functionality is included to maintain compatibility with earlier designs.)
It is assumed that software flow control and hardware flow control will never be enabled
simultaneously. Figure 7
shows an example of software flow control.
SC16IS752_SC16IS762 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 9 — 22 March 2012 12 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
Fig 7. Example of software flow control
TRANSMIT FIFO
PARALLEL-TO-SERIAL
SERIAL-TO-PARALLEL
Xon1 WORD
Xon2 WORD
Xoff1 WORD
Xoff2 WORD
RECEIVE FIFO
PARALLEL-TO-SERIAL
SERIAL-TO-PARALLEL
Xon1 WORD
Xon2 WORD
Xoff1 WORD
Xoff2 WORD
UART2UART1
002aaa229
data
Xoff–Xon–Xoff
compare
programmed
Xon-Xoff
characters

SC16IS752IBS,128

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC I2C/SPI-UARTBRIDGE
Lifecycle:
New from this manufacturer.
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