SC16IS752_SC16IS762 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 9 — 22 March 2012 49 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
Table 39. SPI-bus timing specifications
All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;
V
DD
=2.5V
0.2 V, T
amb
=
40
Cto+85
C; or V
DD
=3.3V
0.3 V, T
amb
=
40
Cto+95
C; V
IL
and V
IH
refer to input
voltage of V
SS
to V
DD
. All output load = 25 pF, unless otherwise specified.
Symbol Parameter Conditions V
DD
=2.5V V
DD
=3.3V Unit
Min Max Min Max
t
TR
CS HIGH to SO 3-state C
L
= 100 pF - 100 - 100 ns
t
CSS
CS to SCLK setup time 100 - 100 - ns
t
CSH
CS to SCLK hold time 5 - 5 - ns
t
DO
SCLK fall to SO valid delay time C
L
= 100 pF - 25 - 20 ns
t
DS
SI to SCLK setup time 10 - 10 - ns
t
DH
SI to SCLK hold time 10 - 10 - ns
t
CP
SCLK period t
CL
+ t
CH
83 - 67 - ns
t
CH
SCLK HIGH time 30 - 25 - ns
t
CL
SCLK LOW time 30 - 25 - ns
t
CSW
CS HIGH pulse width 200 - 200 - ns
t
d9
SPI output data valid time 200 - 200 - ns
t
d10
SPI modem output data valid time 200 - 200 - ns
t
d11
SPI transmit interrupt clear time 200 - 200 - ns
t
d12
SPI modem input interrupt clear time 200 - 200 - ns
t
d13
SPI interrupt clear time 200 - 200 - ns
t
d14
SPI receive interrupt clear time 200 - 200 - ns
t
w(rst)
reset pulse width 3 - 3 - s
Fig 30. Detailed SPI-bus timing
t
CSH
t
CSS
t
CL
t
CH
t
CSH
t
DO
t
TR
t
DS
t
DH
SO
SI
SCLK
CS
002aab066
t
CSW
