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SC16IS752_SC16IS762 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 9 — 22 March 2012 21 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
[1] These registers are accessible only when LCR[7] = logic 0.
[2] This bit can only be modified if register bit EFR[4] is enabled.
[3] These bits are reserved and should be set to logic 0.
[4] After Receive FIFO or Transmit FIFO reset (through FCR [1:0]), the user must wait at least 2 T
clk
of XTAL1 before reading or writing data to RHR and THR respectively.
[5] Burst reads on the serial interface (that is, reading multiple elements on the I
2
C-bus without a STOP or repeated START condition, or reading multiple elements on the SPI bus
without de-asserting the CS
pin), should not be performed on the IIR register.
[6] These registers are accessible only when EFR[4] = logic 1, and MCR[2] = logic 1.
[7] These registers apply to both channels.
[8] IrDA mode slow/fast for SC16IS762, slow only for SC16IS752.
[9] The Special Register set is accessible only when LCR[7] = logic 1 and LCR is not 0xBF.
[10] Enhanced Features Registers are only accessible when LCR = 0xBF.
Special register set
[9]
0x00 DLL bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
0x01 DLH bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
Enhanced register set
[10]
0x02 EFR Auto CTS Auto RTS special
character
detect
enable
enhanced
functions
software flow
control bit 3
software flow
control bit 2
software flow
control bit 1
software flow
control bit 0
R/W
0x04 XON1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
0x05 XON2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
0x06XOFF1bit 7bit 6bit 5bit 4bit 3 bit 2 bit 1bit 0R/W
0x07XOFF2bit 7bit 6bit 5bit 4bit 3 bit 2 bit 1bit 0R/W
Table 10. SC16IS752/SC16IS762 internal registers
…continued
Register
address
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W
