SC16IS752_SC16IS762 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 9 — 22 March 2012 14 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
7.5 Interrupts
The SC16IS752/SC16IS762 has interrupt generation and prioritization (seven prioritized
levels of interrupts) capability. The interrupt enable registers (IER and IOIntEna) enable
each of the seven types of interrupts and the IRQ
signal in response to an interrupt
generation. When an interrupt is generated, the IIR indicates that an interrupt is pending
and provides the type of interrupt through IIR[5:0]. Table 6
summarizes the interrupt
control functions.
It is important to note that for the framing error, parity error, and break conditions, Line
Status Register bit 7 (LSR[7]) generates the interrupt. LSR[7] is set when there is an error
anywhere in the RX FIFO, and is cleared only when there are no more errors remaining in
the FIFO. LSR[4:2] always represent the error status for the received character at the top
of the RX FIFO. Reading the RX FIFO updates LSR[4:2] to the appropriate status for the
new character at the top of the FIFO. If the RX FIFO is empty, then LSR[4:2] are all zeros.
For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt
is cleared by an Xon flow character detection. If a special character detection caused the
interrupt, the interrupt is cleared by a read of the IIR.
Table 6. Summary of interrupt control functions
IIR[5:0] Priority
level
Interrupt type Interrupt source
00 0001 none none none
00 0110 1 receiver line status Overrun Error (OE), Framing Error (FE), Parity Error
(PE), or Break Interrupt (BI) errors occur in
characters in the RX FIFO
00 1100 2 RX time-out stale data in RX FIFO
00 0100 2 RHR interrupt receive data ready (FIFO disable) or
RX FIFO above trigger level (FIFO enable)
00 0010 3 THR interrupt transmit FIFO empty (FIFO disable) or
TX FIFO passes above trigger level (FIFO enable)
00 0000 4 modem status change of state of modem input pins
11 0000 5 I/O pins input pins change of state
01 0000 6 Xoff interrupt receive Xoff character(s)/special character
10 0000 7 CTS
, RTS RTS pin or CTS pin change state from active (LOW)
to inactive (HIGH)
