SC16IS752IBS,128 Datasheet SC16IS752IPW,112, SC16IS762IBS,128, SC16IS762IPW,112 | P34-P36

Product data sheet Rev. 9 — 22 March 2012 34 of 60

NXP Semiconductors

SC16IS752; SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

9.3 Auto RS-485

EFCR bit 0 is used to enable the RS-485 mode (multidrop or 9-bit mode). In this mode of

operation, a ‘master’ station transmits an address character followed by data characters

for the addressed ‘slave’ stations. The slave stations examine the received data and

interrupt the controller if the received character is an address character (parity bit = 1).

To use the auto RS-485 RTS

mode the software would have to disable the hardware flow

control function.

9.3.1 Normal multidrop mode

The 9-bit mode in EFCR (bit 0) is enabled, but not Special Character Detect (EFR bit 5).

The receiver is set to Force Parity 0 (LCR[5:3] = 111) in order to detect address bytes.

With the receiver initially disabled, it ignores all the data bytes (parity bit = 0) until an

address byte is received (parity bit = 1). This address byte will cause the UART to set the

parity error. The UART will generate a line status interrupt (IER bit 2 must be set to ‘1’ at

this time), and at the same time puts this address byte in the RX FIFO. After the controller

examines the byte it must make a decision whether or not to enable the receiver; it should

enable the receiver if the address byte addresses its ID address, and must not enable the

receiver if the address byte does not address its ID address.

If the controller enables the receiver, the receiver will receive the subsequent data until

being disabled by the controller after the controller has received a complete message

from the ‘master’ station. If the controller does not disable the receiver after receiving a

message from the ‘master’ station, the receiver will generate a parity error upon receiving

another address byte. The controller then determines if the address byte addresses its ID

address, if it is not, the controller then can disable the receiver. If the address byte

addresses the ‘slave’ ID address, the controller take no further action; the receiver will

receive the subsequent data.

9.3.2 Auto address detection

If Special Character Detect is enabled (EFR[5] is set and XOFF2 contains the address

byte) the receiver will try to detect an address byte that matches the programmed

character in XOFF2. If the received byte is a data byte or an address byte that does not

match the programmed character in XOFF2, the receiver will discard these data. Upon

receiving an address byte that matches the XOFF2 character, the receiver will be

automatically enabled if not already enabled, and the address character is pushed into the

RX FIFO along with the parity bit (in place of the parity error bit). The receiver also

generates a line status interrupt (IER bit 2 must be set to 1 at this time). The receiver will

then receive the subsequent data from the ‘master’ station until being disabled by the

controller after having received a message from the ‘master’ station.

If another address byte is received and this address byte does not match XOFF2

character, the receiver will be automatically disabled and the address byte is ignored. If

the address byte matches XOFF2 character, the receiver will put this byte in the RX FIFO

along with the parity bit in the parity error bit (LSR[2]).

Product data sheet Rev. 9 — 22 March 2012 35 of 60

NXP Semiconductors

SC16IS752; SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

10. I

C-bus operation

The two lines of the I

C-bus are a serial data line (SDA) and a serial clock line (SCL). Both

lines are connected to a positive supply via a pull-up resistor, and remain HIGH when the

bus is not busy. Each device is recognized by a unique address whether it is a

microcomputer, LCD driver, memory or keyboard interface and can operate as either a

transmitter or receiver, depending on the function of the device. A device generating a

message or data is a transmitter, and a device receiving the message or data is a

receiver. Obviously, a passive function like an LCD driver could only be a receiver, while a

microcontroller or a memory can both transmit and receive data.

10.1 Data transfers

One data bit is transferred during each clock pulse (see Figure 12). The data on the SDA

line must remain stable during the HIGH period of the clock pulse in order to be valid.

Changes in the data line at this time will be interpreted as control signals. A HIGH-to-LOW

transition of the data line (SDA) while the clock signal (SCL) is HIGH indicates a START

condition, and a LOW-to-HIGH transition of the SDA while SCL is HIGH defines a STOP

condition (see Figure 13

). The bus is considered to be busy after the START condition

and free again at a certain time interval after the STOP condition. The START and STOP

conditions are always generated by the master.

The number of data bytes transferred between the START and STOP condition from

transmitter to receiver is not limited. Each byte, which must be eight bits long, is

transferred serially with the most significant bit first, and is followed by an acknowledge bit

(see Figure 14

). The clock pulse related to the acknowledge bit is generated by the

master. The device that acknowledges has to pull down the SDA line during the

acknowledge clock pulse, while the transmitting device releases this pulse (see

Figure 15

Fig 12. Bit transfer on the I

C-bus

Fig 13. START and STOP conditions

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

mba608

SDA

SCL

STOP condition

START condition

Product data sheet Rev. 9 — 22 March 2012 36 of 60

NXP Semiconductors

SC16IS752; SC16IS762

Dual UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

A slave receiver must generate an acknowledge after the reception of each byte, and a

master must generate one after the reception of each byte clocked out of the slave

transmitter. When designing a system, it is necessary to take into account cases when

acknowledge is not received. This happens, for example, when the addressed device is

busy in a real-time operation. In such a case the master, after an appropriate ‘time-out’,

should abort the transfer by generating a STOP condition, allowing other transfers to take

place. These ‘other transfers’ could be initiated by other masters in a multimaster system,

or by this same master.

There are two exceptions to the ‘acknowledge after every byte’ rule. The first occurs when

a master is a receiver: it must signal an end of data to the transmitter by not signalling an

acknowledge on the last byte that has been clocked out of the slave. The acknowledge

related clock generated by the master should still take place, but the SDA line will not be

pulled down. In order to indicate that this is an active and intentional lack of

acknowledgement, we shall term this special condition as a ‘negative acknowledge’.

The second exception is that a slave will send a negative acknowledge when it can no

longer accept additional data bytes. This occurs after an attempted transfer that cannot be

accepted.

Fig 14. Data transfer on the I

C-bus

S P

SDA

SCL

MSB

0 1 6 7 8 0 1 2 to 7 8

ACK ACK

002aab012

START

condition

STOP

condition

acknowledgement signal

from receiver

byte complete,

interrupt within receiver

clock line held LOW

while interrupt is serviced

Fig 15. Acknowledge on the I

C-bus

01 678

002aab013

data output

by transmitter

data output

by receiver

SCL from master

START

condition

transmitter stays off of the bus

during the acknowledge clock

acknowledgement signal

from receiver

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SC16IS752IBS,128

Mfr. #:

Buy SC16IS752IBS,128

Manufacturer:

NXP Semiconductors

Description:

UART Interface IC I2C/SPI-UARTBRIDGE

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SC16IS752IBS,128

SC16IS752IBS,128

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