SC16IS752_SC16IS762 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 9 — 22 March 2012 6 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
6.2 Pin description
Table 2. Pin description
Symbol Pin Type Description
TSSOP28 HVQFN32
CS
/A0 10 7 I SPI chip select or I
2
C-bus device address select A0. If SPI configuration
is selected by I2C/SPI pin, this pin is the SPI chip select pin
(Schmitt-trigger active LOW). If I
2
C-bus configuration is selected by
I2C/SPI
pin, this pin along with A1 pin allows user to change the device’s
base address.
To select the device address, please refer to Table 32
.
CTSA
2 31 I UART clear to send (active LOW), channel A. A logic 0 (LOW) on the
CTSA
pin indicates the modem or data set is ready to accept transmit
data from the SC16IS752/SC16IS762. Status can be tested by reading
MSR[4]. This pin only affects the transmit and receive operations when
Auto-CTS
function is enabled via the Enhanced Features Register
EFR[7] for hardware flow control operation.
CTSB
16 15 I UART clear to send (active LOW), channel B. A logic 0 on the CTSB pin
indicates the modem or data set is ready to accept transmit data from the
SC16IS752/SC16IS762. Status can be tested by reading MSR[4]. This
pin only affects the transmit and receive operations when Auto-CTS
function is enabled via the Enhanced Features Register EFR[7] for
hardware flow control operation.
I2C/SPI
96II
2
C-bus or SPI interface select. I
2
C-bus interface is selected if this pin is
at logic HIGH. SPI interface is selected if this pin is at logic LOW.
IRQ
15 14 O Interrupt (open-drain, active LOW). Interrupt is enabled when interrupt
sources are enabled in the Interrupt Enable Register (IER). Interrupt
conditions include: change of state of the input pins, receiver errors,
available receiver buffer data, available transmit buffer space, or when a
modem status flag is detected. An external resistor (1 k for 3.3 V,
1.5 k for 2.5 V) must be connected between this pin and V
DD
.
SI/A1 11 8 I SPI data input pin or I
2
C-bus device address select A1. If SPI
configuration is selected by I2C/SPI pin, this is the SPI data input pin. If
I
2
C-bus configuration is selected by I2C/SPI pin, this pin along with the
A0 pin allows user to change the slave base address. To select the
device address, please refer to Table 32
.
SO 12 9 O SPI data output pin. If SPI configuration is selected by I2C/SPI
pin, this is
a 3-stateable output pin. If I
2
C-bus configuration is selected by the
I2C/SPI
pin, this pin is undefined and must be left as not connected.
SCL/SCLK 13 10 I I
2
C-bus or SPI input clock.
SDA 14 11 I/O I
2
C-bus data input/output, open-drain if I
2
C-bus configuration is selected
by I2C/SPI
pin. If SPI configuration is selected, this is not used and must
be connected to V
SS
.
GPIO0/DSRB
18 17 I/O Programmable I/O pin or modem DSRB
[1]
GPIO1/DTRB 19 18 I/O Programmable I/O pin or modem DTRB
[1]
GPIO2/CDB 20 19 I/O Programmable I/O pin or modem CDB
[1]
GPIO3/RIB 21 20 I/O Programmable I/O pin or modem RIB
[1]
GPIO4/DSRA 25 24 I/O Programmable I/O pin or modem DSRA
[2]
GPIO5/DTRA 26 25 I/O Programmable I/O pin or modem DTRA
[2]
GPIO6/CDA 27 26 I/O Programmable I/O pin or modem CDA
[2]
GPIO7/RIA 28 27 I/O Programmable I/O pin or modem RIA
[2]
