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SC16IS752IBS,128

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60
SC16IS752_SC16IS762 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 9 — 22 March 2012 7 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
[1] Selectable with IOControl register bit 2.
[2] Selectable with IOControl register bit 1.
[3] See Section 7.4 “
Hardware Reset, Power-On Reset (POR) and Software Reset”.
[4] HVQFN32 package die supply ground is connected to both V
SS
pins and exposed center pad. V
SS
pins must be connected to supply
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
[5] XTAL2 should be left open when XTAL1 is driven by an external clock.
RESET 5 2 I Hardware reset (active LOW)
[3]
RTSA 1 30 O UART request to send (active LOW), channel A. A logic 0 on the RTSA
pin indicates the transmitter has data ready and waiting to send. Writing a
logic 1 in the Modem Control Register MCR[1] will set this pin to a logic 0,
indicating data is available. After a reset this pin is set to a logic 1. This
pin only affects the transmit and receive operations when Auto-RTS
function is enabled via the Enhanced Features Register (EFR[6]) for
hardware flow control operation.
RTSB
17 16 O UART request to send (active LOW), channel B. A logic 0 on the RTSB
pin indicates the transmitter has data ready and waiting to send. Writing a
logic 1 in the Modem Control Register MCR[1] will set this pin to a logic 0,
indicating data is available. After a reset this pin is set to a logic 1. This
pin only affects the transmit and receive operations when Auto-RTS
function is enabled via the Enhanced Features Register (EFR[6]) for
hardware flow control operation.
RXA 4 1 I Channel A receiver input. During the local Loopback mode, the RXA
input pin is disabled and TXA data is connected to the UART RXA input
internally.
RXB 24 23 I Channel B receiver input. During the local Loopback mode, the RXB
input pin is disabled and TXB data is connected to the UART RXB input
internally.
TXA 3 32 O Channel A transmitter output. During the local Loopback mode, the TXA
output pin is disabled and TXA data is internally connected to the UART
RXA input.
TXB 23 22 O Channel B transmitter output. During the local Loopback mode, the TXB
output pin is disabled and TXB data is internally connected to the UART
RXB input.
V
DD
8 5, 13, 28 - Power supply
V
SS
22 12, 21,
29
[4]
- Ground
V
SS
-center
pad
[4]
- The center pad on the back side of the HVQFN32 package is metallic
and should be connected to ground on the printed-circuit board.
XTAL1 6 3 I Crystal input or external clock input. A crystal can be connected between
XTAL1 and XTAL2 to form an internal oscillator circuit (see Figure 11
).
Alternatively, an external clock can be connected to this pin.
XTAL2 7 4 O Crystal output. (See also XTAL1.) XTAL2 is used as a crystal oscillator
output
[5]
.
Table 2. Pin description
…continued
Symbol Pin Type Description
TSSOP28 HVQFN32
SC16IS752_SC16IS762 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 9 — 22 March 2012 8 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
7. Functional description
The UART will perform serial-to-I
2
C-bus conversion on data characters received from
peripheral devices or modems, and I
2
C-bus-to-serial conversion on data characters
transmitted by the host. The complete status of the SC16IS752/SC16IS762 UART can be
read at any time during functional operation by the host.
The SC16IS752/SC16IS762 can be placed in an alternate mode (FIFO mode) relieving
the host of excessive software overhead by buffering received/transmitted characters.
Both the receiver and transmitter FIFOs can store up to 64 characters (including three
additional bits of error status per character for the receiver FIFO) and have selectable or
programmable trigger levels.
The SC16IS752/SC16IS762 has selectable hardware flow control and software flow
control. Hardware flow control significantly reduces software overhead and increases
system efficiency by automatically controlling serial data flow using the RTS
output and
CTS
input signals. Software flow control automatically controls data flow by using
programmable Xon/Xoff characters.
The UART includes a programmable baud rate generator that can divide the timing
reference clock input by a divisor between 1 and (2
16
1).
7.1 Trigger levels
The SC16IS752/SC16IS762 provides independently selectable and programmable trigger
levels for both receiver and transmitter interrupt generation. After reset, both transmitter
and receiver FIFOs are disabled and so, in effect, the trigger level is the default value of
one character. The selectable trigger levels are available via the FIFO Control Register
(FCR). The programmable trigger levels are available via the Trigger Level Register
(TLR). If TLR bits are cleared, then selectable trigger level in FCR is used. If TLR bits are
not cleared, then programmable trigger level in TLR is used.
7.2 Hardware flow control
Hardware flow control is comprised of Auto-CTS and Auto-RTS (see Figure 4). Auto-CTS
and Auto-RTS
can be enabled/disabled independently by programming EFR[7:6].
With Auto-CTS
, CTS must be active before the UART can transmit data.
Auto-RTS
only activates the RTS output when there is enough room in the FIFO to
receive data and de-activates the RTS
output when the RX FIFO is sufficiently full. The
halt and resume trigger levels in the Transmission Control Register (TCR) determine the
levels at which RTS
is activated/deactivated. If TCR bits are cleared, then selectable
trigger levels in FCR are used in place of TCR.
If both Auto-CTS
and Auto-RTS are enabled, when RTS is connected to CTS, data
transmission does not occur unless the receiver FIFO has empty space. Thus, overrun
errors are eliminated during hardware flow control. If not enabled, overrun errors occur if
the transmit data rate exceeds the receive FIFO servicing latency.
SC16IS752_SC16IS762 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 9 — 22 March 2012 9 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
7.2.1 Auto-RTS
Figure 5 shows RTS functional timing. The receiver FIFO trigger levels used in Auto-RTS
are stored in the TCR. RTS
is active if the RX FIFO level is below the halt trigger level in
TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTS
is de-asserted. The
sending device (for example, another UART) may send an additional character after the
trigger level is reached (assuming the sending UART has another character to send)
because it may not recognize the de-assertion of RTS
until it has begun sending the
additional character. RTS
is automatically reasserted once the receiver FIFO reaches the
resume trigger level programmed via TCR[7:4]. This re-assertion allows the sending
device to resume transmission.
Fig 4. Auto flow control (Auto-RTS and Auto-CTS) example
RX
FIFO
FLOW
CONTROL
TX
FIFO
PARALLEL
TO SERIAL
TX
FIFO
RX
FIFO
UART 1 UART 2
RX TX
RTS CTS
TX RX
CTS RTS
002aab656
SERIAL TO
PARALLEL
SERIAL TO
PARALLEL
FLOW
CONTROL
FLOW
CONTROL
FLOW
CONTROL
PARALLEL
TO SERIAL
(1) N = receiver FIFO trigger level.
(2) The two blocks in dashed lines cover the case where an additional character is sent, as described in Section 7.2.1
.
Fig 5. RTS functional timing
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60

SC16IS752IBS,128

Mfr. #:
Buy SC16IS752IBS,128
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC I2C/SPI-UARTBRIDGE
Lifecycle:
New from this manufacturer.
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