SC16IS752_SC16IS762 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 9 — 22 March 2012 40 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
The register read cycle (see Figure 19) commences in a similar manner, with the master
sending a slave address with the direction bit set to WRITE with a following subaddress.
Then, in order to reverse the direction of the transfer, the master issues a Repeated
START followed again by the device address, but this time with the direction bit set to
READ. The data bytes starting at the internal subaddress will be clocked out of the device,
each followed by a master-generated acknowledge. The last byte of the read cycle will be
followed by a negative acknowledge, signalling the end of transfer. The cycle is
terminated by a STOP signal.
White block: host to SC16IS752/SC16IS762
Grey block: SC16IS752/SC16IS762 to host
(1) See Table 33
for additional information.
Fig 18. Master writes to slave
S SLAVE ADDRESS
002aab047
W A REGISTER ADDRESS
(1)
A n DATA A P
White block: host to SC16IS752/SC16IS762
Grey block: SC16IS752/SC16IS762 to host
(1) See Table 33
for additional information.
Fig 19. Master read from slave
S SLAVE ADDRESS
002aab048
W A REGISTER ADDRESS
(1)
A
NA P
S SLAVE ADDRESS R A
nDATA A LAST DATA
Table 33. Register address byte (I
2
C)
Bit Name Function
7 - not used
6:3 A[3:0] UART’s internal register select
2:1 CH1, CH0 Channel select.
00 = channel A
01 = channel B
10 = reserved
11 = reserved
0 - not used
