LH79524/LH79525 System-on-Chip
18 Version 1.0 Data Sheet for Rev. A.1 Silicon
SYSTEM DESCRIPTIONS
ARM720T Processor
The LH79524/LH79525 microcontrollers feature
the ARM720T cached core with an Advanced High-Per-
formance Bus (AHB) interface. The ARM720T features:
• 32-bit ARM720T RISC Core
• 8KB Cache
• MMU (Windows CE enabled)
The core processor for both is a member of the
ARM7T family of processors. For more information, see
the ARM document, ‘ARM720T (Rev 3) Technical
Reference Manual’, available on ARM’s website at
www.ARM.com.
The LH79524/LH79525 MMU allows mapping Phys-
ical Memory (PA) addresses to virtual memory
addresses. This allows physical memory, which is
constrained by hardware to specific addresses, to be
reorganized at addresses identified by the user. These
user identified locations are called Virtual Addresses
(VA). When the MMU is enabled, Code and Data must
be built, loaded, and executed using Virtual Addresses
which the MMU translates to Physical Addresses. In
addition, the user may implement a memory protection
scheme by using the features of the MMU. Address
translation and memory protection services provided
by the MMU are controlled by the user. The MMU
is directly controlled through the System Control
Coprocessor, Coprocessor 15 (CP15). The MMU is
indirectly controlled by a Translation Table (TT) and
Page Tables (PT) prepared by the user and estab-
lished using a portion of physical memory dedicated by
the user to storing the TT and PT’s.
Figure 2. LH79524/LH79525 Application Diagram Example
STN/TFT,
AD-TFT
LCD
TOUCH SCREEN
GPIO SSP
A/D
KEY
MATRIX
SERIAL
EEPROM
ETHERNET
MAC
A/D
UART
I
2
S
FLASH
SRAM or
SDRAM
BOOT
ROM
UART
USB
LH79524/LH79525
ETHERNET
TRANSCEIVER
SENSOR
ARRAY
LH79525-19A
1 2 3
4 5 6
7 8 9
*
0 #
CODEC
WIRELESS
ROUTER/
SWITCHER
