System-on-Chip LH79524/LH79525
Data Sheet for Rev. A.1 Silicon Version 1.0 7
P11 PN3/D25 I/O General Purpose I/O Signals — Port N3; multiplexed with Data bit D25
J2 nRESETIN I Reset Input
H1 nRESETOUT O Reset Output
C16 XTALIN I Crystal Input
C15 XTALOUT O Crystal Output
D16 XTAL32IN I 32.768 kHz Crystal Oscillator Input
D15 XTAL32OUT O 32.768 kHz Crystal Oscillator Output
K1 CLKOUT O Clock Out (selectable from the internal bus clock or 32.768 kHz crystal)
D2 nTRST I JTAG Test Reset Input
P4 TMS I JTAG Test Mode Select Input
T3 TCK I JTAG Test Clock Input
T1 TDI I JTAG Test Serial Data Input
P3 TDO O JTAG Test Data Serial Output
T2 TEST1 I Tie HIGH for Normal Operation; pull LOW to enable Embedded ICE Debugging
R3 TEST2 I Tie HIGH for Normal Operation; pull HIGH to enable Embedded ICE Debugging
E3 LINREGEN I Linear Regulator Enable
D5, E4,
E5, H13,
N5
VDDC Power Core Power Supply
D10, F4,
J13, N4
VSSC
Ground Core GND
D7, D8,
D9, F13,
G4,
G13, H4,
J4, K4,
K13, L4,
N6, N8,
N9, N10
VDD Power Input/Output Power Supply
E12, G8,
G9, H7,
H8, H9,
H10, J7,
J8, J9,
J10, K8,
K9, M5
VSS
Ground Input/Output GND
D1 VDDA0 Power Analog Power Supply for Analog-to-Digital Converter
F16 VDDA1 Power Analog Power Supply for the USB PLL
E16 VDDA2 Power Analog Power Supply for System PLL
J1 VSSA0
Ground
Analog GND for Analog-to-Digital Converter
F15 VSSA1
Ground
Analog GND for the USB PLL
E15 VSSA2
Ground
Analog GND for System PLL
Table 1. LH79524 Pin Descriptions (Cont’d)
CABGA
PIN
SIGNAL NAME TYPE DESCRIPTION
