LH79524/LH79525 System-on-Chip
20 Version 1.0 Data Sheet for Rev. A.1 Silicon
DMA Controller
The DMA Controller provides support for DMA-
capable peripherals. The LCD controller uses its own
DMA port, connecting directly to memory for retrieving
display data.
• Simultaneous servicing of up to 4 data streams
• Three transfer modes are supported:
– Memory to Memory
– Peripheral to Memory
– Memory to Peripheral
• Identical source and destination capabilities
• Transfer Size Programmable (byte, half-word, word)
• Burst Size Programmable
• Address Increment or Address Freeze
• Transfer Error interrupt for each stream
• 16-word FIFO array with pack and unpack logic
Handles all combinations of byte, half-word or word
transfers from input to output.
Color LCD Controller (CLCDC)
The CLCDC provides all the necessary control and
drive signals to interface directly with a variety of color
and monochrome LCD panels.
• LH79524 has 16 LCD Data bits; LH79525 has 12
LCD Data bits.
• Supports single and dual scan color and mono-
chrome Super Twisted Nematic (STN) displays with
4- or 8-bit interfaces (LH79524 only)
• Supports Thin Film Transistor (TFT) color displays
• Programmable resolution up to 1,024 × 1,024
• 15 gray-level mono, 3,375 color STN, and 64 k color
TFT support
• 1, 2, or 4 bits-per-pixel (BPP) for monochrome STN
• 1-, 2-, 4-, or 8-BPP palettized color displays for color
STN and TFT (1-, 2-, or 4-bit only on LH79525)
• True-color non-palettized, for color STN and TFT
• Programmable timing for different display panels
• 256-entry, 16-bit palette fast-access RAM
• Frame, line and pixel clock signals
• AC bias signal for STN or data enable signal for
TFT panels
• Patented grayscale algorithm
• Interrupt Generation Events
• Dual 16-deep programmable 32-bit wide FIFOs for
buffering incoming data.
ADVANCED LCD INTERFACE
The Advanced LCD Interface (ALI) allows for direct
connection to ultra-thin panels that do not include a tim-
ing ASIC. It converts TFT signals from the Color LCD
controller to provide the proper signals, timing and levels
for direct connection to a panel’s Row and Column driv-
ers for AD-TFT, HR-TFT, or any technology of panel that
allows for a connection of this type. The Advanced LCD
Interface peripheral also provides a bypass mode that
allows the LH79524/LH79525 to interface to the built-in
timing ASIC in standard TFT and STN panels.
Synchronous Serial Port (SSP)
The SSP is a master or slave interface for synchro-
nous serial communication with master or slave periph-
eral devices that support protocols for Motorola SPI,
National Semiconductor MICROWIRE, or Texas
Instruments Synchronous Serial Interface.
• Master or slave operation
• Programmable clock rate
• Separate transmit FIFO and receive FIFO buffers,
16 bits wide, 8 locations deep
• DMA for transmit and receive
• Programmable interface protocols: Motorola SPI,
National Semiconductor MICROWIRE, or Texas
Instruments Synchronous Serial Port
• Programmable data frame size from 4 to 16 bits
• Independent masking of transmit FIFO, receive
FIFO and receive overrun interrupts
• Available internal loopback test mode.
Figure 6. Memory Remap ‘11’
LH79525-18
ADVANCED HIGH-PERFORMANCE BUS
PERIPHERALS
ADVANCED PERIPHERAL BUS
PERIPHERALS
RESERVED
EXTERNAL SRAM nCS0
REMAP = 11
EXTERNAL STATIC MEMORY
EXTERNAL SDRAM
16KB INTERNAL SRAM
BOOT ROM
RESERVED
0xFFFFFFFF
0xFFFF1000
0xFFFF0000
0xFFFC0000
0xA0000000
0x80000000
0x60000000
0x40000000
0x20000000
0x00000000
