System-on-Chip LH79524/LH79525
Data Sheet for Rev. A.1 Silicon Version 1.0 53
UNUSED INPUT SIGNAL CONDITIONING
Floating input signals can cause excessive power
consumption. Unused inputs which do not include inter-
nal pull-up or pull-down resistors should be pulled up or
down externally, to tie the signal to its inactive state.
Some GPIO signals may default to inputs. If the pins
which carry these signals are unused, software can
program these signals as outputs, to eliminate the need
for pull-ups or pull-downs. Power consumption may be
higher than expected until such software executes.
Some LH79524/LH79525 inputs have internal pull-
ups or pull-downs. If unused, these inputs do not
require external conditioning.
OTHER CIRCUIT BOARD LAYOUT PRACTICES
All output pins on the LH79524/LH79525 have fast
rise and fall times. Printed circuit trace interconnection
length must therefore be reduced to minimize over-
shoot, undershoot and reflections caused by transmis-
sion line effects of these fast output switching times.
This recommendation particularly applies to the
address and data buses.
When considering capacitance, calculations must
consider all device loads and capacitances due to the
circuit board traces. Capacitance due to the traces will
depend upon a number of factors, including the trace
width, dielectric material the circuit board is made from
and proximity to ground and power planes.
Attention to power supply decoupling and printed cir-
cuit board layout becomes more critical in systems with
higher capacitive loads. As these capacitive loads
increase, transient currents in the power supply and
ground return paths also increase.
Add pull-ups to all unused inputs unless an
internal pull-down resistor has been specified; see
Table 2. Consider all signals that are Inputs at Reset.
SUGGESTED EXTERNAL COMPONENTS
Figure 37 shows the suggested external compo-
nents for the 32.768 kHz crystal circuit to be used with
the SHARP LH79524/LH79525. The NAND gate rep-
resents the logic inside the SoC. See the table in
Figure 37 for crystal specifics.
Figure 38 shows the suggested external compo-
nents for the 10 - 20 MHz crystal circuit to be used with
the SHARP LH79524/LH79525. The NAND gate
represents the logic inside the SoC. See the chart for
crystal specifics.
Figure 37. Suggested External Components, 32.768 kHz Oscillator (XTAL32IN and XTAL32OUT)
ENABLE
XTAL32IN XTAL32OUT
INTERNAL TO
THE LH79524/LH79525
EXTERNAL TO
THE LH79524/LH79525
GND
NOTES:
1. Y1 is a parallel-resonant type crystal. (See table)
2. The nominal values for C1 and C2 shown are for
a crystal specified at 12.5 pF load capacitance (CL).
3. The values for C1 and C2 are dependent upon
the cystal's specified load capacitance and PCB
stray capacitance.
4. R1 must be in the circuit.
5. Ground connections should be short and return
to the ground plane which is connected to the
processor's core ground pins.
6. Tolerance for R1, C1, C2 is ≤ 5%.
GND
32.768 kHz
10 MΩ
LH79525-11
PARAMETER
RECOMMENDED CRYSTAL SPECIFICATIONS
DESCRIPTION
32.768 kHz Crystal
Tolerance
Aging
Load Capacitance
ESR (MAX.)
Drive Level
Recommended Part
Parallel Mode
±30 ppm
±3 ppm
12.5 pF
50 kΩ
1.0 μW (MAX.)
MTRON SX1555 or equivalent
C1
15 pF
C2
18 pF
R1
Y1
