LH79524/LH79525 System-on-Chip
28 Version 1.0 Data Sheet for Rev. A.1 Silicon
Table 13. AC Signal Characteristics
SIGNAL TYPE LOAD SYMBOL MIN. MAX. DESCRIPTION
ASYNCHRONOUS MEMORY INTERFACE SIGNALS
A[27:0]
Output 50 pF tWC 3 × tHCLK – 5.0 ns Write Cycle time
Input tRC 2 × tHCLK – 5.0 ns Read Cycle time
D[31:0] Output 50 pF
tDHWE tHCLK – 5.5 ns Data out hold to nWE release
tDWE tHCLK – 4.5 ns Data out valid to nWE release
tDSCS 14.0 ns Data valid to nCSx release
tDSOE 12.5 ns Data valid to nOE release
tDSB 12.0 ns Data valid to nBLEx release
tDHCS 0.0 ns nCSx release to data invalid
tDHOE 0.0 ns nOE release to data invalid
nCS[3:0] Output 50 pF
tAV 2.5 ns nCSx valid to Address valid
tAHCS tHCLK – 3.0 ns Address hold after nCSx release
tAHOE tHCLK - 1.0 ns Address hold after nOE release
tASCS 2.5 ns Address valid to nCSx valid
tCW 2 × tHCLK + 3.0 ns nCSx valid to nWE release
tCB 2 × tHCLK nCSx valid to nBLE release
tCS tHCLK – 3.5 ns nCSx width
nBLE Output 50 pF
tBV 1.5 ns nCSx valid to nBLE valid
tAHB tHCLK – 2.0 ns Address hold after nBLE release
tDB tHCLK – 6.0 ns Data out valid to nBLE release
tDHBR 0.0 ns Data in hold to nBLE release
tDHBW tHCLK + 9 ns Data out hold to nBLE release
tBR –2.0 ns Address hold to nBLE release
tAB 2 × tHCLK ns Address valid to nBLE release
tASB 1.0 ns Address valid to nBLE valid
tBLE tHCLK – 4.5 ns nBLE width (read)
tBP tHCLK – 4.5 ns nBLE width (write)
nWE Output 50 pF
tASWE tHCLK + 1.5 ns Address valid to nWE valid
tAW 2 × tHCLK + 0.5 ns Address valid to nWE release
tWR tHCLK – 3.0 ns Address Hold to nWE release
tWP tHCLK – 1 ns Write Enable width
nOE Output 50 pF
tOE tHCLK – 1 ns Ouput Enable width
tOEV – 0.5 ns nOE valid after nCSx valid
SYNCHRONOUS MEMORY INTERFACE SIGNALS
A[23:0] Ouput 50 pF tOVA tSDCLK/2 + 4.5 ns Address Valid
D[31:0]
Output 50 pF
tOVD tSDCLK/2 + 7.0 ns Output Data Valid
tOHD tSDCLK/2 – 4.0 ns Output Data Hold
Input
tISD 5.0 ns Input Data Setup
tIHD 1.5 ns Input Data Hold
nCAS Output 50 pF
tOVCA tSDCLK/2 + 4.0 ns CAS Valid
tOHCA tSDCLK/2 – 4.0 ns CAS Hold
nRAS Output 50 pF
tOVRA tSDCLK/2 + 4.5 ns RAS Valid
tOHRA tSDCLK/2 – 4.0 ns RAS Hold
