LH79524N0F100A0 Datasheet LH79525N0Q100A0, LH79524N0E100A0, LH79524N0F100A0 | P25-P27

System-on-Chip LH79524/LH79525

Data Sheet for Rev. A.1 Silicon Version 1.0 25

ADC and Brownout Detector

The ADC block consists of an 10-channel, 10-bit

Analog-to-Digital Converter with integrated Touch

Screen Controller (TSC). The complete touch screen

interface is achieved by combining the front-end bias-

ing, control circuitry with analog-to-digital conversion,

reference generation, and digital control.

The ADC has a bias-and-control network that allows

correct operation with both 4- and 5-wire touch panels.

A 16-entry × 16-bit wide FIFO holds a 10-bit ADC

output and a 4-bit tag number.

When the screen is touched, it pushes the conduc-

tive coating on the coversheet against the coating

on the glass, making electrical contact. The voltages

produced are the analog representation of the position

touched. The voltage level of the coversheet is

converted continuously by the ADC and monitored by

the system.

Other features include:

• 10-bit fully differential Successive Approximation

• A 10-channel multiplexer that routes user-selected

inputs to the ADC in single-ended and differential

modes

• A 16-entry × 16-bit wide FIFO that holds the 10-bit

ADC output

• Front bias-and-control network for touch screen

interface and support functions, which are compati-

ble with industry-standard 4- and 5-wire touch-sensi-

tive panels

• Touch-pressure sensing circuits

• Pen-down sensing circuit and interrupt generator

• Independent voltage reference generator

• Conversion automation function to minimize

interrupt overhead

• Brownout Detector

• Battery Control Signal.

ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings

NOTE: These stress ratings are only for transient conditions. Oper-

ation at or beyond absolute maximum rating conditions may

affect reliability and cause permanent damage to the device.

Recommended Operating Conditions

NOTES:

1. Linear Regulator disabled.

2. With PLL enabled. Without PLL, minimum frequency is 0 MHz.

Some peripherals may not operate at minimum frequency.

3. Choose 11.2896 MHz to ensure proper operation of the I

S, USB,

and UART peripherals.

4. Core Voltage should never exceed I/O Voltage after initial power

up. See “Power Supply Sequencing” on page 26.

PARAMETER SYMBOL RATING UNIT

DC Core Supply Voltage VDDC -0.3 to 2.4 V

DC I/O Supply Voltage VDD -0.3 to 4.6 V

DC Analog Supply

Voltage for ADC

VDDA0 -0.3 to 4.6 V

VDDA1 -0.3 to 2.4 V

VDDA2 -0.3 to 2.4 V

Storage Temperature TSTG -55 to +125 °C

PARAMETER MINIMUM TYPICAL MAXIMUM NOTES

DC Core Supply Voltage (VDDC) 1.7 V 1.8 V 1.9 V 1, 4

DC I/O Supply Voltage (VDD) 3.0 V 3.3 V 3.6 V 4

DC Analog Supply Voltage (VDDA0) 3.0 V 3.3 V 3.6 V

DC Analog Supply Voltage (VDDA1) 1.7 V 1.8 V 1.9 V

DC Analog Supply Voltage (VDDA2) 1.7 V 1.8 V 1.9 V

Clock Frequency 3.27 MHz 76.205 MHz 2

Crystal Frequency 10.0 MHz 11.2896 MHz 20.0 MHz 3

Operating Temperature (Industrial) -40°C 25°C +85°C

LH79524/LH79525 System-on-Chip

26 Version 1.0 Data Sheet for Rev. A.1 Silicon

Power Supply Sequencing

When the linear regulator is not enabled, SHARP

recommends that the 1.8 V power supply be energized

before the 3.3 V supply. If this is not possible, the 1.8 V

supply may not lag the 3.3 V supply by more than 100

μs. If longer delay time is needed, it is recommended

that the voltage difference between the two power sup-

plies be within 1.5 V during power supply ramp up. To

avoid a potential latchup condition, voltage should be

applied to input pins only after the device is powered-

on as described above.

DC/AC Specifications

Unless noted, all data provided are based on:

• -40°C to +85°C (Industrial temperature range)

• VDDC = 1.7 V to 1.9 V

• VDD = 3.0 V to 3.6 V, VDDA = 1.7 V to 1.9 V.

DC SPECIFICATIONS

NOTES:

1. Table 2 details each pin’s buffer type.

2. Running Typical Application over operating range.

3. Current measured with CPU stopped and all peripherals enabled

Linear Regulator DC Characteristics.

SYMBOL PARAMETER MIN. TYP. MAX. UNIT CONDITIONS

VIH CMOS input HIGH voltage 2.0 5.5 V CEN = 1

VIL CMOS input LOW voltage 0.8 V CEN = 1

VIT+ Positive Input threshold voltage (Schmitt pins) 2.0 V CSEN = 1

VIT- Negative Input threshold voltage (Schmitt pins) 0.8 V CSEN = 1

VHYST Schmitt trigger hysteresis 0.35 V CSEN = 1

VOH

Output drive (2 mA type) 2.6 V IOH = -2 mA

Output drive (4 mA type) 2.6 V IOH = -4 mA

Output drive (8 mA type) 2.6 V IOH = -8 mA

Output drive (12 mA type) 2.6 V IOH = -12 mA

VOL

Output drive (2 mA type) 0.4 V IOL = 2 mA

Output drive (4 mA type) 0.4 V IOL = 4 mA

Output drive (8 mA type) 0.4 V IOL = 7 mA

Output drive (12 mA type) 2.6 V IOH = 12 mA

RIN Input leakage pull-up/pull-down resistors 40 kΩ

VIN = VDD or GND (Calculate input

leakage current at desired VDD)

IACTIVE Active current 85 mA Note 2

ISTANDBY Standby current 50 mA Notes 2, 3

ISLEEP Sleep current 3.8 mA

ISTOP1 Stop1 current 420 μA

ISTOP2 Stop2 current 115 μA RTC ON, Linear Regulator ON

ISTOP2 Stop2 current 95 μA RTC OFF, Linear Regulator ON

ISTOP2 Stop2 current 45 μA RTC ON, Linear Regulator OFF

ISTOP2 Stop2 current 25 μA RTC OFF, Linear Regulator OFF

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

IQUIESCENT Quiescent Current 75 μA

ISLEEPLR Current with Linear Regulator disabled 8 μA

IOLR Output Current Range 0.0 200 mA

VOLR Output Voltage, Linear Regulator 1.84 V

System-on-Chip LH79524/LH79525

Data Sheet for Rev. A.1 Silicon Version 1.0 27

AC Test Conditions

Power Consumption By Peripheral Device

Table 12 shows the typical power consumption by

individual peripheral device.

AC Specifications

All signals described in Table 13 relate to transitions

after a reference clock signal. The illustration in Figure

7 represents all cases of these sets of measurement

parameters; except for the Asynchronous Memory

Interface — which are referenced to Address Valid.

The reference clock signals in this design are:

• HCLK, the System Bus clock

• PCLK, the Peripheral Bus clock (locked to HCLK in

the LH79524/LH79525)

• SSPCLK, the Synchronous Serial Interface clock

• UARTCLK, the UART Interface clock

• LCDDCLK, the LCD Data clock from the

LCD Controller

• and SDCLK, the SDRAM clock.

All signal transitions are measured from the 50%

point of the clock to the 50% point of the signal. See

Figure 7.

For outputs from the LH79524/LH79525, tOVXXX

(e.g. tOVA) represents the amount of time for the out-

put to become valid from the rising edge of the refer-

ence clock signal. Maximum requirements for tOVXXX

are shown in Table 13.

The signal tOHXXX (e.g. tOHA) represents the

amount of time the output will be held valid from the ris-

ing edge of the reference clock signal. Minimum

requirements for tOHXXX are listed in Table 13.

For Inputs, tISXXX (e.g. tISD) represents the

amount of time the input signal must be valid before the

rising edge of the clock signal. Minimum requirements

for tISXXX are shown in Table 13.

The signal tIHXXX (e.g. tIHD) represents the

amount of time the output must be held valid from the

rising edge of the reference clock signal. Minimum

requirements are shown in Table 13.

PARAMETER RATING UNIT

Supply Voltage (VDD) 3.0 to 3.6 V

Core Voltage (VDDC) 1.7 to 1.9 V

Input Pulse Levels VSS to VDD V

Input Rise and Fall Times 2 ns

Input and Output Timing

Reference Levels

VDD/2 V

Table 12. Peripheral Current Consumption

PERIPHERAL TYPICAL UNITS

ADC/TSC 590

μA

Counter/Timers 203 μA

DMA 4.2 mA

Ethernet Controller 670 μA

S 200 μA

LCD Controller 2.2 mA

RTC 5.1 μA

SSP 508 μA

UARTs 203

μA

USB Device (+PLL) 5.6 (+3.3) mA

Figure 7. LH79524/LH79525 Signal Timing

REFERENCE

CLOCK

OUTPUT

SIGNAL (O)

INPUT

SIGNAL (I)

tOVXXX

tOHXXX

tISXXX tIHXXX

LH79525-28

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57 P58-P59

LH79524N0F100A0

Mfr. #:

Buy LH79524N0F100A0

Manufacturer:

Description:

IC MCU 32BIT ROMLESS 208CABGA

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

LH79524N0F100A0

LH79524N0F100A0

Products related to this Datasheet