LH79524N0F100A0 Datasheet LH79525N0Q100A0, LH79524N0E100A0, LH79524N0F100A0 | P46-P48

LH79524/LH79525 System-on-Chip

46 Version 1.0 Data Sheet for Rev. A.1 Silicon

Figure 27. STN Vertical Timing

VDD

See

Note 2

DISPLAY-DEPENDENT

TURN-ON DELAY

1 STN FRAME

PANEL POSITIVE HIGH-VOLTAGE SUPPLY ACTIVE

PANEL NEGATIVE HIGH-VOLTAGE SUPPLY ACTIVE

PANEL LOGIC ACTIVE

PANEL DATA CLOCK ACTIVE

DATA ENABLE

SEE 'STN HORIZONTAL TIMING DIAGRAM'

ENUMERATED IN

HORIZONTAL 'LINES'

FRONT PORCH

ALL 'LINES' FOR ONE FRAME

VSS

LCDVDDEN

(DIGITAL SUPPLY

ENABLE FOR

HIGH-VOLTAGE

SUPPLIES)

LCDDCLK

(PANEL CLOCK)

TIMING2:PCD

TIMING2: BCD

TIMING2: IPC

TIMING2: CPL

LCDEN

(DATA ENABLE)

TIMING2:ACB

TIMING2: IOE

LCDFP

(VERTICAL

SYNCHRONIZATION

PULSE)

TIMING1: IVS

(See Note 3)

PIXEL DATA AND

HORIZONTAL

CONTROL

SIGNALS FOR

ONE FRAME

NOTES:

1. Signal polarties may vary for some displays.

2. See 'STN horizontal timing' diagram.

3. LCDFP with TIMING1:VSW = 0 is only a single horizontal ine period.

DISPLAY

DEPENDENT

TURN-OFF DELAY

TIMING1: LPP TIMING1: VFP

TIMING1: VSW = 1

LH79525-44

System-on-Chip LH79524/LH79525

Data Sheet for Rev. A.1 Silicon Version 1.0 47

Figure 28. TFT Horizontal Timing

VDD

See

Note 2

DISPLAY-DEPENDENT

TURN-ON DELAY

1 TFT FRAME

PANEL POSITIVE HIGH-VOLTAGE SUPPLY ACTIVE

PANEL NEGATIVE HIGH-VOLTAGE SUPPLY ACTIVE

PANEL LOGIC ACTIVE

PANEL DATA CLOCK ACTIVE

DATA ENABLE

BACK PORCH

ENUMERATED IN

HORIZONTAL 'LINES'

SEE 'TFT HORIZONTAL TIMING DIAGRAM'

ENUMERATED IN

HORIZONTAL 'LINES'

FRONT PORCHALL 'LINES' FOR ONE FRAME

VSS

LCDVDDEN

(DIGITAL SUPPLY

ENABLE)

LCDDCLK

(PANEL CLOCK)

TIMING2:PCD

TIMING2: BCD

TIMING2: IPC

LCDEN

(DATA ENABLE)

TIMING2:ACB

TIMING2: IOE

LCDFP

(VERTICAL

SYNCHRONIZATION

PULSE)

TIMING1: IVS

PIXEL DATA AND

HORIZONTAL

CONTROL

SIGNALS FOR

ONE FRAME

NOTES:

1. Signal polarties may vary for some displays.

2. The use of LCDDSPLEN for high-voltage power control is optional on some TFT panels.

DISPLAY

DEPENDENT

TURN-OFF DELAY

TIMING1: VBP TIMING1: LPP TIMING1: VFP

TIMING1: VSW

LH79525-40

LH79524/LH79525 System-on-Chip

48 Version 1.0 Data Sheet for Rev. A.1 Silicon

Figure 29. TFT Vertical Timing

VDD

See

Note 2

DISPLAY-DEPENDENT

TURN-ON DELAY

1 TFT FRAME

PANEL POSITIVE HIGH-VOLTAGE SUPPLY ACTIVE

PANEL NEGATIVE HIGH-VOLTAGE SUPPLY ACTIVE

PANEL LOGIC ACTIVE

PANEL DATA CLOCK ACTIVE

DATA ENABLE

BACK PORCH

ENUMERATED IN

HORIZONTAL 'LINES'

SEE 'TFT HORIZONTAL TIMING DIAGRAM'

ENUMERATED IN

HORIZONTAL 'LINES'

FRONT PORCHALL 'LINES' FOR ONE FRAME

VSS

LCDVDDEN

(DIGITAL SUPPLY

ENABLE)

LCDDCLK

(PANEL CLOCK)

TIMING2:PCD

TIMING2: BCD

TIMING2: IPC

LCDEN

(DATA ENABLE)

TIMING2:ACB

TIMING2: IOE

LCDFP

(VERTICAL

SYNCHRONIZATION

PULSE)

TIMING1: IVS

PIXEL DATA AND

HORIZONTAL

CONTROL

SIGNALS FOR

ONE FRAME

NOTES:

1. Signal polarties may vary for some displays.

2. The use of LCDDSPLEN for high-voltage power control is optional on some TFT panels.

DISPLAY

DEPENDENT

TURN-OFF DELAY

TIMING1: VBP TIMING1: LPP TIMING1: VFP

TIMING1: VSW

LH79525-40

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57 P58-P59

LH79524N0F100A0

Mfr. #:

Buy LH79524N0F100A0

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Description:

IC MCU 32BIT ROMLESS 208CABGA

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LH79524N0F100A0

LH79524N0F100A0

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