LH79524N0F100A0 Datasheet LH79525N0Q100A0, LH79524N0E100A0, LH79524N0F100A0 | P22-P24

LH79524/LH79525 System-on-Chip

22 Version 1.0 Data Sheet for Rev. A.1 Silicon

Reset, Clock, and Power Controller (RCPC)

The RCPC generates the various clock signals for the

operation of the LH79524/LH79525 and provides for an

orderly start-up after power-on and during a wake-up

from one of the power saving operating modes. The

RCPC allows the software to individually select the fre-

quency of the various on-chip clock signals as required

to operate the chip in the most power-efficient mode.

The maximum speeds of the various clocks in the SoC

are shown in Table 10. More detailed descriptions of

each clock appear in the User’s Guide.

The RCPC features:

• 10 - 20 MHz crystal oscillator and PLL for on-chip

Clock generation (11.2896 MHz recommended)

• External Clock input if on-chip oscillator and PLL are

not used

• 32.768 kHz crystal oscillator generating 1 Hz clock

for Real Time Clock

• Individually controlled clocks for peripherals and CPU

• Programmable clock prescalers for UARTs and PWMs

• Five global power control modes are available:

– Active

– Standby

–Sleep

–Stop1

–Stop2

• CPU/Bus clock frequency can be changed on the fly

• Selectable clock output

• Hardware reset (nRESETIN) and software reset.

Real Time Clock

The RTC provides an alarm or long time base

counter. An interrupt is generated following counting a

programmed number of one-second periods. The 1 Hz

RTC clock is internally derived. The RTC features:

• 32-bit up counter with programmable load

• Programmable 32-bit match compare register

• Software maskable interrupt when counter and com-

pare registers are identical.

RTC input clock sources:

• PLL clock

• 32.768 kHz clock

• 1 Hz clock (default).

18 ADC Pen IRQ

19 CLCD Combined Interrupt

20 DMA Stream 0

21 DMA Stream 1

22 DMA Stream 2

23 DMA Stream 3

24 SSP I

S Interrupt

25 Ethernet Interrupt

26 USB Interrupt

27 UART 0 Interrupt

28 UART 1 Interrupt

29 UART 2 Interrupt

30 USB DMA Interrupt

31 I

C Interrupt

Table 9. Interrupt Channels (Cont’d)

CHANNEL INTERRUPT SOURCE

Table 10. Maximum Clock Speeds

NAME

FREQUENCY

(MAX.)

Oscillator Clock (CLK OSC) 20.0 MHz

PLL System Clock (CLK PLL) 304.819 MHz

PLL USB Clock 48.0 MHz

32.768 kHz Oscillator Clock 32.768 kHz

AHB Clock (HCLK) 50.803 MHz

AHB Fast CPU Clock (FCLK CPU) 76.205 MHz

Ethernet Clock 50.803 MHz

DMA Clock 50.803 MHz

External Memory Controller Clock 50.803 MHz

SSP Clock 50.803 MHz

CLCD Clock 50.803 MHz

UART[2:0] Clock 20.0 MHz

RTC Clock 1.0 Hz

Table 11. Clock Activity for Different Power Modes

DEVICE ACTIVE STANDBY SLEEP STOP1 STOP2

RTC 32 kHz

Oscillator

ON ON ON ON ON

10 - 20 MHz

Oscillator

ON ON ON ON OFF

PLL ON ON ON OFF OFF

Peripheral

Clock

ON ON OFF OFF OFF

CPU Clock ON OFF OFF OFF OFF

System-on-Chip LH79524/LH79525

Data Sheet for Rev. A.1 Silicon Version 1.0 23

Watchdog Timer

The Watchdog Timer provides hardware protection

against malfunctions. It is a programmable timer to be

reset by software at regular intervals. Failure to reset

the timer will cause a FIQ interrupt. Failure to service

the FIQ interrupt will then generate a System Reset.

The features of the Watchdog Timer are:

• Driven by the bus clock

• 16 programmable time-out periods: 2

through 2

clock cycles

• Generates a reset or an FIQ Interrupt whenever a

time-out period is reached

• Software enable, lockout, and counter-reset mecha-

nisms add security against inadvertent writes

• Protection mechanism guards against interrupt-ser-

vice failure:

– The first WDT time-out triggers FIQ and asserts

nWDFIQ status flag

– If FIQ service routine fails to clear nWDFIQ, then

the next WDT time-out triggers a system reset.

Timers

The LH79524 and LH79525 incorporate three 16-bit

independently programmable Timer modules. The tim-

ers are clocked by the system clock, but have an inter-

nal scaled-down system clock that is used for the Pulse

Width Modulator (PWM) and compare functions.

All counters are incremented by an internal pre-

scaled counter clock or external clock and can gener-

ate an overflow interrupt. All three timers have separate

internal prescaled counter clocks, with either a com-

mon external clock or a prescaled version of the sys-

tem clock.

• Timer 0 has five Capture Registers and two Com-

pare Registers.

• Timer 1 and Timer 2 have two Capture and two Com-

pare Registers each.

The Capture Registers have edge-selectable inputs

and can generate an interrupt. The Compare Registers

can force the compare output pin either HIGH or LOW

upon a match.

The timers support a PWM Mode that uses the two

Timer Compare Registers associated with a timer to

create a PWM. Each timer can generate a separate

interrupt. The interrupt becomes active if any enabled

compare, capture, or overflow interrupt condition

occurs. The interrupt remains active until all compare,

capture, and overflow interrupts are cleared.

General Purpose Input/Output (GPIO)

The LH79524 provides up to 108 bits of programma-

ble input/output, and the LH79525 provides 86 bits.

Many of the GPIO pins are multiplexed with other sig-

nals. All GPIO feature:

• Individually programmable input/output pins

• All default to Input on power-up.

• LH79524

– Ports A-I, K, L, and N: Bidirectional I/O (Port N is

4 bits wide)

– Port J: Input only

– Port M: Output only

• LH79525

– Ports A-I: Bidirectional I/O

– Port J: Input only

– Port M: Output only (6 bits wide)

Boot Controller

The boot controller allows selection of the hardware

device to be used for booting.

• Supports booting from 8-, 16-, or 32-bit devices,

selectable via external pins at power-on reset

• Configures the byte lane boot state for nCS1,

selectable via external pins at power-on reset.

• Supports booting from alternate external devices

(e.g., NAND flash) via external pins on power-on reset

• Glueless interface to external NAND flash.

USB Device

The USB Device integrated into the LH79524/

LH79525 is compliant with the USB 1.1 and 2.0 speci-

fication, and compatible with both the OpenHCI and

Intel UHCI standards. The USB Device:

• Supports Full-Speed (12 Mbit/s) operation, and

suspend and resume signaling

• Four Endpoints

• Bulk/Interrupt or Isochronous Transfers

• FIFO for each Endpoint direction (except EP0 which

shares a FIFO between IN/OUT). FIFOs exist in

2464 × 8 RAM

• Supports DMA accesses to FIFO.

LH79524/LH79525 System-on-Chip

24 Version 1.0 Data Sheet for Rev. A.1 Silicon

Ethernet MAC Controller

The on-board Ethernet MAC Controller (EMAC) is

compatible with IEEE 802.3, and has passed the Uni-

versity of New Hampshire (UNH) testing. It supports

both 10- and 100-Mbit/s, and full and half duplex oper-

ation. Other features include:

• Statistics counter registers for RMON/MIB

• MII interface to the physical layer

• Interrupt generation to signal receive and transmit

completion

• Transmit and receive FIFOs

• Automatic pad and CRC generation on transmitted

frames

• Automatic discard of frames received with errors

• Address checking logic supports up to four specific

(hardware) 48-bit addresses

• Supports promiscuous mode where all valid

received frames are copied to memory

• Hash matching of unicast and multicast destination

addresses

• Supports physical layer management through MDIO

interface

• Supports serial network interface operation

• Support for:

– Half duplex flow control by forcing collisions on in-

coming frames

– Full duplex flow control with recognition of incom-

ing pause frames and hardware generation of

transmitted pause frames

– 802.Q VLAN tagging with recognition of incoming

VLAN and priority tagged frames

• Multiple buffers per receive and transmit frame

• Software configures the MAC address

• Jumbo frames of up to 10,240 bytes supported.

C Controller

The I

C Controller includes a two-wire I

C serial

interface capable of operating in either Master or Slave

mode. The block conforms to the I

C 2.1 Bus Specifi-

cation for data rates up to 400 kbit/s. The two wires are

SCL (serial clock) and SDA (serial data). The I

C mod-

ule provides the following features:

• Two-wire synchronous serial interface

• Operates in both the standard mode, for data rates

up to 100 kbit/s, and the fast mode, with data rates

up to 400 kbit/s

• Communicates with devices in the fast mode as well

as the standard mode if both are attached to the bus.

SSP To I

S Converter

The SSP to I

S converter is an interface that con-

verts a synchronous serial communication stream in TI

DSP-compatible mode into an I

S compliant synchro-

nous serial stream. The I

S converter operates on

serial data in both master and slave mode.

The I

S converter provides:

• Programmable Word Select (WS) delay

• Left/right channel information:

– Current WS value at the pin

– WS value associated with next entry written to

TX FIFO

– WS value associated with next entry read from

RX FIFO

• Ability to invert WS state

• Ability to invert the bit clock

• Supports frame size of 16 bits only. Any other frame

size will result in a frame size error. Each frame

transmits starting with the most-significant bit.

• Master and slave modes supported

• As with the SSP, a single combined interrupt is gen-

erated as an OR function of the individual interrupt

requests. This interrupt replaces the SSP interrupt,

which is used solely as an input to the I

S converter.

• Additional interrupts:

– Transmit FIFO underrun

– Transmit frame size error

– Receive frame size error

• A set of Interrupt registers contain all the information

in the SSPIMSC, SSPRIS, and SSPMIS registers,

plus the transmit underrun error and frame size errors

• Additional status bits:

– Transmit FIFO Full

– Receive FIFO Empty

• Passes SSP data unaltered when module is not

enabled

• Loopback Test Mode support.

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LH79524N0F100A0

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