LH79524/LH79525 System-on-Chip
42 Version 1.0 Data Sheet for Rev. A.1 Silicon
External DMA Handshake Signal Timing
DREQ TIMING
Once asserted, DREQ must not transition from LOW
to HIGH again until after nDACK has been asserted.
DACK/DEOT TIMING
These timing diagrams indicate when nDACK and
DEOT occur in relation to an external bus access to/from
the external peripheral that requested the DMA transfer.
The first diagram shows the timing with relation to a
single read or the last word of a burst read from the
requesting peripheral. The remaining diagrams show
timing for data transfers.
Figure 21. DREQ Timing Restrictions
Figure 22. Read, from Peripheral to Memory, Burst Size = 1
DREQ
MUST NOT
TRANSITON
DREQ MAY
TRANSITON
tDREQ0L,
tDREQ1L
DREQ0,
DREQ1
DACK0
nDACK1
NOTE: tDREQ0L = DREQ0 LOW Pulse Width = 2 HCLK MIN.
tDREQ1L = DREQ1 LOW Pulse Width = 2 HCLK MIN.
LH79525-5
HCLK
(See Note)
A[23:0]
ADDRESS
DATA
D[31:0]
nCSx
nWEN
nBLE[1:0]
nOE
DACK0/
DEOT0/DEOT1
nDACK1
NOTE: * HCLK is an internal signal provided for reference only.
LH79525-6
