System-on-Chip LH79524/LH79525
Data Sheet for Rev. A.1 Silicon Version 1.0 35
NOTES:
1. The timing relationship is specified as a cycle-based timing. Variations caused by clock jitter, power rail noise, and I/O condtioning will cause
these timings to vary nominally. It is recommended that designers add a small margin to avoid possible corner-case conditions.
2. The Write Wait States register (SWAITWRx) must be set to a minimum value of 3.
3. For each rising clock edge (HCLK) that the assertion of nWAIT lags the assertion of nCSx, another write wait state (SWAITRDx) must be
added to the minimum requirement.
4. nWAIT delay cycles are not added for all nWAIT assertions sampled prior to WST-3. These nWAIT assertions are ignored.
5. nWAIT delay cycles are added for all nWAIT assertions sampled from WST-3 until the de-assertion of nWAIT. nWAIT delay cycles are added
once the wait state countdown has reached WST-1.
6. Once nWAIT is sampled high, the current memory transaction is queued to complete.
7. Since static and dynamic memory cannot be accessed at the same time, any prolonged access (either due to nWAIT or the Extended Wait
Register) that causes an SDRAM refresh failure may cause SDRAM data to be lost.
8. Timing assumes Write Enable Delay register (SWAITWENx) is programmed to 0.
Figure 12. nWAIT Write Sequence (SWAITWRx = 3)
Table 16. nWAIT Write Sequence Parameter Definitions
PARAMETER DESCRIPTION MIN. MAX. UNIT
1
tIDA_nCS(x)_nWAIT Delay from nCS(x) assertion to nWAIT assertion 0 16,365 HCLK periods
tDD_nWAIT_nCS(x) Delay from nWAIT deassertion to nCS(x) deassertion 6 HCLK periods
tDD_nWAIT_nWE Delay from nWAIT deassertion to nWE deassertion 5 HCLK periods
tA_nWAIT Assertion time of nWAIT 2 HCLK periods
tDA_nCS(x)_nWAIT
HCLK
nCS(x)
nWE
nWAIT
NOTES:
SQ: nWAIT Sampled and Queued
SI: nWAIT Sampled and Ignored
tA_nWAIT
SQ-4 SQ-3 SQ-2 SQ-1 SQ-0
tDD_nWAIT_nCS(x)
tDD_nWAIT_nWE
LH79525-136
WST-3
DELAY
WST-2
DELAY
WST-1
DELAY
SQ-4
nWAIT
DELAY
SQ-3
nWAIT
DELAY
SQ-2
nWAIT
DELAY
SQ-1
nWAIT
DELAY
SQ-0
nWAIT
DELAY
WST-0
DELAY
END
CYCLE
nWE
END
CYCLE
nCS(x)
Transaction
Sequence
