ZL50017 Data Sheet
10
Zarlink Semiconductor Inc.
K3 234 TMS Test Mode Select (5 V-Tolerant Input with Internal Pull-up)
JTAG signal that controls the state transitions of the TAP
controller. This pin is pulled high by an internal pull-up resistor
when it is not driven.
L4 238 TCK Test Clock (5 V-Tolerant Schmitt-Triggered Input with Internal
Pull-up)
Provides the clock to the JTAG test logic.
L3 239 TRST
Test Reset (5 V-Tolerant Input with Internal Pull-up)
Asynchronously initializes the JTAG TAP controller by putting it in
the Test-Logic-Reset state. This pin should be pulsed low during
power-up to ensure that the device is in the normal functional
mode. When JTAG is not being used, this pin should be pulled low
during normal operation.
M3 240 TDi Test Serial Data In (5 V-Tolerant Input with Internal Pull-up)
JTAG serial test instructions and data are shifted in on this pin.
This pin is pulled high by an internal pull-up resistor when it is not
driven.
G5 212 TDo Test Serial Data Out (5 V-Tolerant Three-state Output)
JTAG serial data is output on this pin on the falling edge of TCK.
This pin is held in high impedance state when JTAG is not
enabled.
B12, B13,
C10, C11,
F13, G4,
K12, C12,
80, 105,
150, 151,
152, 153,
210, 149
IC_Open Internal Test Mode (5 V-Tolerant Input with Internal
Pull-down)
These pins may be left unconnected.
G3, D12,
C13, B14
144, 107,
148, 208
IC_GND Internal Test Mode Enable (5 V-Tolerant Input)
These pins MUST be low.
PBGA Pin
Number
LQFP Pin
Number
Pin Name Description
ZL50017 Data Sheet
11
Zarlink Semiconductor Inc.
A8, A9, A14,
A15, E10,
M2, N2, P2,
P16, R2,
R16, T6, T7,
T8, T9, T10,
T11, T12,
T13, T14,
T15, D16,
E16, C16,
B16, A13,
A12, A10,
A11, N1,
M1, P1, R1,
T2, T3, T5,
T4, N16,
M16, L16,
K16, H16,
J16, G16,
F16,D9, E8,
C8, E7, D6,
H5, P10,
G15, G14,
E15, F14,
H14, D11,
F15, B7, C7,
B5, J6, R3,
P6, R5, N5,
P12, N15,
P13, P15,
E1, D1, G1,
F1, J1, H1,
K1, L1, A7,
A5, A6, A4,
A3, A2, C1,
B1, E9, D8,
B8, D7
61, 62,
63, 64,
65, 66,
67, 68,
134, 135,
136, 137,
138, 139,
140, 215,
219, 225,
229, 236,
237, 125,
126, 127,
128, 129,
130, 131,
132, 253,
254, 255,
256, 1, 2,
3, 4, 75,
76, 77,
78, 119,
120, 122,
124,159,
163, 165,
167, 176,
221, 43,
102, 106,
110, 112,
100, 104,
108, 170,
172, 174,
227, 11,
12, 13,
14, 55,
56, 58,
59, 243,
244, 245,
246, 247,
248, 250,
252, 189,
190, 191,
192, 193,
194, 196,
197, 161,
164, 166,
168
NC No Connect
These pins MUST be left unconnected.
PBGA Pin
Number
LQFP Pin
Number
Pin Name Description
ZL50017 Data Sheet
12
Zarlink Semiconductor Inc.
M14, R13 46, 48 MODE_4M0,
MODE_4M1
4 M Input Clock Mode 0 to 1 (5 V-Tolerant Input with internal
pull-down) These two pins should be tied together.
See Table 4, “Control Register (CR) Bits” on page 28 for CKi and
FPi selection using the CKIN1 - 0 bits.
B10 155 FPi ST-BUS/GCI-Bus Frame Pulse Input (5 V-Tolerant
Schmitt-Triggered Input)
This pin accepts the frame pulse which stays active for 61 ns,
122 ns or 244 ns at the frame boundary. The frame pulse
frequency is 8 kHz. The frame pulse associated with the CKi must
be applied to this pin. By default, the device accepts a negative
frame pulse in ST-BUS format, but it can accept a positive frame
pulse instead if the FPINP bit is set high in the Control Register
(CR). It can accept a GCI-formatted frame pulse by programming
the FPINPOS bit in the Control Register (CR) to high.
B11 154 CKi ST-BUS/GCI-Bus Clock Input (5 V-Tolerant Schmitt-Triggered
Input)
This pin accepts a 4.096 MHz, 8.192 MHz or 16.384 MHz clock.
The clock frequency applied to this pin must be twice the highest
input or output data rate. The exception is, when data is running
at 16.384 Mbps, a 16.384 MHz clock must be used.
By default, the clock falling edge defines the input frame
boundary, but the device allows the clock rising edge to define the
frame boundary by programming the CKINP bit in the Control
Register (CR).
B6, C6, D5,
D4, B4, B3,
C5, C4, E3,
C2, B2, D2,
F3, F4, E2,
F2
179, 180,
181, 182,
183, 184,
185, 187,
198, 200,
201, 202,
203, 204,
205, 206
STi0 - 15 Serial Input Streams 0 to 15 (5 V-Tolerant Inputs with Internal
Pull-downs)
The data rate of all the input streams are programmed through the
“Data Rate Selection Register” on page 31. In the 2.048 Mbps
mode, these pins accept serial TDM data streams at 2.048 Mbps
with 32 channels per frame. In the 4.096 Mbps mode, these pins
accept serial TDM data streams at 4.096 Mbps with 64 channels
per frame. In the 8.192 Mbps mode, these pins accept serial TDM
data streams at 8.192 Mbps with 128 channels per frame. In the
16.384 Mbps mode, these pins accept serial TDM data streams
at 16.384 Mbps with 256 channels per frame.
PBGA Pin
Number
LQFP Pin
Number
Pin Name Description
MODE
_4M1
MODE
_4M0
Operation
00
CKi = 8.192 MHz or 16.384 MHz
11
CKi = 4.096 MHz
01 Reserved
10 Reserved

ZL50017GAG2

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Digital Bus Switch ICs Pb Free Basic 1K DX
Lifecycle:
New from this manufacturer.
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