ZL50017 Data Sheet
7
Zarlink Semiconductor Inc.
1.0 Pinout Diagrams
1.1 BGA Pinout
Figure 2 - ZL50017 256-Ball 17 mm x 17 mm PBGA (as viewed through top of package)
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A
V
SS
NC NC NC NC NC NC NC NC NC NC NC NC NC NC V
SS
A
B
NC STi10 STi5 STi4 NC STi0 NC NC
V
DD_
COREA
FPi CKi IC_Open IC_Open IC_GND ODE NC
B
C
NC STi9 V
SS
STi7 STi6 STi1 NC NC V
SS
IC_Open IC_Open IC_Open IC_GND V
SS
STio15 NC
C
D
NC STi11 V
DD_IO
STi3 STi2 NC NC NC NC V
SS
NC IC_GND STio13 V
DD_IO
STio14 NC
D
E
NC STi14 STi8 V
DD_IO
V
SS
V
DD_
CORE
NC NC NC NC
V
DD_
CORE
V
SS
V
DD_IO
STio12 NC NC
E
F
NC STi15 STi12 STi13 V
DD_IO
V
DD_
CORE
V
DD_
CORE
V
SS
V
SS
V
DD_
CORE
V
DD_
CORE
V
DD_IO
IC_Open NC NC NC
F
G
NC RESET IC_GND IC_Open TDo V
DD_IO
V
SS
V
SS
V
SS
V
SS
V
DD_IO
A12 A13 NC NC NC
G
H
NC V
SS
V
SS
V
DD_
COREA
NC V
SS
V
SS
V
SS
V
SS
V
SS
A7 A9 A10 NC A11 NC
H
J
NC V
DD_IOA
V
DD_IOA
V
SS
V
SS
NC V
SS
V
SS
V
SS
V
SS
A3 A4 A5 A8 A6 NC
J
K
NC V
SS
TMS V
SS
V
DD_
COREA
V
DD_IO
V
SS
V
SS
V
SS
V
SS
V
DD_IO
IC_Open A0 A2 A1 NC
K
L
NC
V
DD_
COREA
TRST TCK V
DD_IO
V
DD_
CORE
V
DD_
CORE
V
SS
V
SS
V
DD_
CORE
V
DD_
CORE
V
DD_IO
STio10 STio11 STio9 NC
L
M
NC NC TDi D0 V
SS
V
DD_
CORE
V
DD_
CORE
D6 D10
V
DD_
CORE
V
DD_
CORE
V
SS
MOT
_INTEL
MODE_
4M0
STio8 NC
M
N
NC NC V
DD_IO
STio0 NC D1 D5 D7 D11 D13
R/W
_WR
DTA_
RDY
STio4 V
DD_IO
NC NC
N
P
NC NC V
SS
STio1 STio3 NC D3 D8 D14 NC STio5 NC NC V
SS
NC NC
P
R
NC NC NC STio2 NC D2 D4 D9 D12 D15 CS DS_RD
MODE_
4M1
STio6 STio7 NC
R
T
V
SS
NC NC NC NC NC NC NC NC NC NC NC NC NC NC V
SS
T
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Note: A1 corner identified by metallized marking.
Note: Pinout is shown as viewed through top of package.
