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ZL50017GAG2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51
ZL50017 Data Sheet
34
Zarlink Semiconductor Inc.
14.0 Memory
14.1 Memory Address Mappings
When A13 is high, the data or connection memory can be accessed by the microprocessor port. Bit 1 - 0 in the
Control Register determine the access to the data or connection memory (CM_L or CM_H).
MSB
(Note 1)
Stream Address
(St0 - 15)
Channel Address
(Ch0 - 255)
A13
A12A11A10 A9 A8 Stream [n] A7A6A5A4A3A2A1A0 Channel [n]
1
1
1
1
1
1
1
1
1
.
.
.
.
.
1
1
0
0
0
0
0
0
0
0
0
.
.
.
.
.
0
0
0
0
0
0
0
0
0
0
1
.
.
.
.
.
1
1
0
0
0
0
1
1
1
1
0
.
.
.
.
.
1
1
0
0
1
1
0
0
1
1
0
.
.
.
.
.
1
1
0
1
0
1
0
1
0
1
0
.
.
.
.
.
0
1
Stream 0
Stream 1
Stream 2
Stream 3
Stream 4
Stream 5
Stream 6
Stream 7
Stream 8
.
.
.
.
.
Stream 14
Stream 15
0
0
.
.
0
0
0
0
.
.
0
0
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.
0
0
.
.
.
.
1
1
0
0
.
.
0
0
0
0
.
.
0
0
.
.
1
1
.
.
.
.
1
1
0
0
.
.
0
0
1
1
.
.
1
1
.
.
1
1
.
.
.
.
1
1
0
0
.
.
1
1
0
0
1
1
.
.
1
1
.
.
.
.
1
1
0
0
.
.
1
1
0
0
.
.
1
1
.
.
1
1
.
.
.
.
1
1
0
0
.
.
1
1
0
0
.
1
1
.
.
1
1
.
.
.
.
1
1
0
0
.
.
1
1
0
0
1
1
.
.
1
1
.
.
.
.
1
1
0
1
.
.
0
1
0
1
.
.
0
1
.
.
0
1
.
.
.
.
0
1
Ch 0
Ch 1
.
.
Ch 30
Ch 31 (Note 2)
Ch 32
Ch 33
.
.
Ch 62
Ch 63 (Note 3)
.
.
Ch126
Ch 127 (Note 4)
.
.
.
.
Ch 254
Ch 255 (Note 5)
Notes:
1. A13 must be high for access to data and connection memory positions. A13 must be low to access internal registers.
2. Channels 0 to 31 are used when serial stream is at 2.048 Mbps.
3. Channels 0 to 63 are used when serial stream is at 4.096 Mbps.
4. Channels 0 to 127 are used when serial stream is at 8.192 Mbps.
5. Channels 0 to 255 are used when serial stream is at 16.384 Mbps.
Table 11 - Address Map for Memory Locations (A13 = 1)
ZL50017 Data Sheet
35
Zarlink Semiconductor Inc.
14.2 Connection Memory Low (CM_L) Bit Assignment
When the CMM bit (bit 0) in the connection memory low is zero, the per-channel transmission is set to the normal
channel-switching. The connection memory low bit assignment for the channel transmission mode is shown in
Table 12 on page 35.
Bit Name Description
15 Unused Reserved
In normal functional mode, these bits MUST be set to zero.
14 V/C
Variable/Constant Delay Control
When this bit is low, the output data for this channel will be taken from con-
stant delay memory.
When this bit is set to high, the output data for this channel will be taken from
variable delay memory. Note that VAREN must be set in Control Register
first.
13 Unused Reserved. In normal functional mode, this bit MUST be set to zero.
12 - 9 SSA3 - 0 Source Stream Address
The binary value of these 4 bits represents the input stream number.
8 - 1 SCA7 - 0 Source Channel Address
The binary value of these 8 bits represents the input channel number.
0 CMM = 0 Connection Memory Mode = 0
If this is low, the connection memory is in the normal switching mode. Bit 13 -
1 are the source stream number and channel number.
Table 12 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0
151413121110987654321 0
0V/C0 SSA
3
SSA
2
SSA
1
SSA
0
SCA
7
SCA
6
SCA
5
SCA
4
SCA
3
SCA
2
SCA
1
SCA
0
CMM
=0
ZL50017 Data Sheet
36
Zarlink Semiconductor Inc.
When CMM is one, the device is programmed to perform one of the special per-channel transmission modes. Bits
PCC0 and PCC1 from connection memory are used to select the per-channel tristate or message mode as shown
in Table 13 on page 36.
Bit Name Description
15 - 11 Unused
Reserved
In normal functional mode, these bits MUST be set to zero.
10 - 3 MSG7 - 0 Message Data Bits
8-bit data for the message mode. Not used in the per-channel tristate.
2 - 1 PCC1 - 0 Per-Channel Control Bits
These two bits control the corresponding entry’s value on the STio stream.
0 CMM = 1 Connection Memory Mode = 1
If this is high, the connection memory is in the per-channel control mode
which is per-channel tristate or per-channel message mode.
Table 13 - Connection Memory Low (CM_L) Bit Assignment when CMM = 1
151413121110987654321 0
0 0000MSG
7
MSG
6
MSG
5
MSG
4
MSG
3
MSG
2
MSG
1
MSG
0
PCC
1
PCC
0
CMM
=1
PC
C1
PC
C0
Channel Output Mode
0 0 Per Channel Tristate
0 1 Message Mode
10 Reserved
11 Reserved
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51

ZL50017GAG2

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Buy ZL50017GAG2
Manufacturer:
Microchip / Microsemi
Description:
Digital Bus Switch ICs Pb Free Basic 1K DX
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New from this manufacturer.
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