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ZL50017GAG2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51
ZL50017 Data Sheet
List of Figures
4
Zarlink Semiconductor Inc.
Figure 1 - ZL50017 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - ZL50017 256-Ball 17 mm x 17 mm PBGA (as viewed through top of package) . . . . . . . . . . . . . . . . . . . 7
Figure 3 - ZL50017 256-Lead 28 mm x 28 mm LQFP (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4 - Input Timing when CKIN1 - 0 bits = “10” in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5 - Input Timing when CKIN1 - 0 bits = “01” in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6 - Input Timing when CKIN1 - 0 = “00” in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 7 - Input Bit Delay Timing Diagram (ST-BUS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8 - Input Bit Sampling Point Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9 - Input Bit Delay and Factional Sampling Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10 - Output Bit Advancement Timing Diagram (ST-BUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 11 - Output Fractional Bit Advancement Timing Diagram (ST-BUS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12 - Data Throughput Delay for Variable Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13 - Data Throughput Delay for Constant Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 14 - Timing Parameter Measurement Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 15 - Motorola Non-Multiplexed Bus Timing - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 16 - Motorola Non-Multiplexed Bus Timing - Write Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 17 - Intel Non-Multiplexed Bus Timing - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 18 - Intel Non-Multiplexed Bus Timing - Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 19 - JTAG Test Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 20 - Frame Pulse Input and Clock Input Timing Diagram (ST-BUS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 21 - Frame Pulse Input and Clock Input Timing Diagram (GCI-Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 22 - ST-BUS Input and Output Timing Diagram when Operated at 2, 4, 8 and 16 Mbps . . . . . . . . . . . . . . 47
Figure 23 - GCI-Bus Input and Output Timing Diagram when Operated at 2, 4, 8 and 16 Mbps . . . . . . . . . . . . . 48
ZL50017 Data Sheet
List of Tables
5
Zarlink Semiconductor Inc.
Table 1 - Delay for Variable Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 2 - Connection Memory Low After Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 3 - Address Map for Registers (A13 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 4 - Control Register (CR) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 5 - Internal Mode Selection Register (IMS) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 6 - Software Reset Register (SRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 7 - Data Rate Selection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 8 - Internal Flag Register (IFR) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 9 - Stream Input Control Register 0 - 15 (SICR0 - 15) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 10 - Stream Output Control Register 0 - 15 (SOCR0 - 15) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 11 - Address Map for Memory Locations (A13 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 12 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 13 - Connection Memory Low (CM_L) Bit Assignment when CMM = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
ZL50017 Data Sheet
6
Zarlink Semiconductor Inc.
Changes Summary
The following table captures the changes from January 2006 to November 2006.
The following table captures the changes from the October 2004 issue.
Page Item Change
1 Updated Ordering Information.
Page Item Change
13 Pin Description “STio 0 - 15” on page 13 • Clarified STio 0-15 pin description.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51

ZL50017GAG2

Mfr. #:
Buy ZL50017GAG2
Manufacturer:
Microchip / Microsemi
Description:
Digital Bus Switch ICs Pb Free Basic 1K DX
Lifecycle:
New from this manufacturer.
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