ZL50017 Data Sheet
28
Zarlink Semiconductor Inc.
13.0 Detailed Register Description
Bit Name Description
15 - 10 Unused Reserved. In normal functional mode, these bits MUST be set to zero.
9FPINPOSInput Frame Pulse (FPi) Position
When this bit is low, FPi straddles frame boundary (as defined by ST-BUS).
When this bit is high, FPi starts from frame boundary (as defined by GCI-Bus)
8CKINPClock Input (CKi) Polarity
When this bit is low, the CKi falling edge aligns with the frame boundary.
When this bit is high, the CKi rising edge aligns with the frame boundary.
7FPINPFrame Pulse Input (FPi) Polarity
When this bit is low, the input frame pulse FPi has the negative frame pulse format.
When this bit is high, the input frame pulse FPi has the positive frame pulse format.
6 - 5 CKIN1 - 0 Input Clock (CKi) and Frame Pulse (FPi) Selection
The MODE_4M0 and MODE_4M1 pins, as described in “Pin Description” on page 9,
should also be set to define the input clock mode.
4 VAREN Variable Delay Mode Enable
When this bit is low, the variable delay mode is disabled on a device-wide basis.
When this bit is high, the variable delay mode is enabled on a device-wide basis.
3 MBPE Memory Block Programming Enable
When this bit is high, the connection memory block programming mode is enabled to
program the connection memory. When it is low, the memory block programming mode is
disabled.
Table 4 - Control Register (CR) Bits
External Read/Write Address: 0000
H
Reset Value: 0000
H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00 0 000FPIN
POS
CKINP FPINP CKIN
1
CKIN
0
VAR
EN
MBPE OSB MS1 MS0
CKIN1 - 0 FPi Active Period CKi
00 61 ns 16.384 MHz
01 122 ns 8.192 MHz
10 244 ns 4.096 MHz
11 Reserved
ZL50017 Data Sheet
29
Zarlink Semiconductor Inc.
2OSBOutput Stand By Bit:
This bit enables the STio0 - 1 serial outputs. The following table describes the HiZ control
of the serial data outputs:
Note: Unused output streams are tristated (STio = HiZ). Refer to SOCR0 - 15 (bit 2 - 0).
1 - 0 MS1 - 0 Memory Select Bits
These two bits are used to select connection memory low, connection high or data mem-
ory for access by CPU:
Bit Name Description
Table 4 - Control Register (CR) Bits (continued)
External Read/Write Address: 0000
H
Reset Value: 0000
H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00 0 000FPIN
POS
CKINP FPINP CKIN
1
CKIN
0
VAR
EN
MBPE OSB MS1 MS0
RESET
Pin
SRSTSW
(in SRR)
ODE
Pin
OSB
Bit
STio0 - 15
0XXX HiZ
11XX HiZ
100X HiZ
1010 HiZ
1011 Active
(Controlled by CM)
MS1 - 0 Memory Selection
00 Connection Memory Low Read/Write
01 Reserved
10 Data Memory Read
11 Reserved
ZL50017 Data Sheet
30
Zarlink Semiconductor Inc.
Bit Name Description
15 - 9 Unused Reserved. In normal functional mode, these bits MUST be set to zero.
8STIO_PD_
EN
STio Pull-down Enable
When this bit is low, the pull-down resistors on all STio pads will be disabled.
When this bit is high, the pull-down resistors on all STio pads will be enabled.
7UnusedReserved. In normal functional mode, these bits MUST be set to zero.
6BDLBi-directional Control
5 - 4 Unused Reserved. In normal functional mode, these bits MUST be set to zero.
3 - 1 BPD2 - 0 Block Programming Data
These bits refer to the value to be loaded into the connection memory, whenever the
memory block programming feature is activated. After the MBPE bit in the Control
Register is set to high and the MBPS bit in this register is set to high, the contents of
the bits BPD2 - 0 are loaded into bits 2 - 0 of the Connection Memory Low. Bits 15 - 3
of the Connection Memory Low.
0 MBPS Memory Block Programming Start:
A zero to one transition of this bit starts the memory block programming function. The
MBPS and BPD2 - 0 bits in this register must be defined in the same write operation.
Once the MBPE bit in the Control Register is set to high, the device requires two
frames to complete the block programming. After the programming function has fin-
ished, the MBPS bit returns to low, indicating the operation is completed. When MBPS
is high, MBPS or MBPE can be set to low to abort the programming operation.
Whenever the microprocessor writes a one to the MBPS bit, the block programming
function is started. As long as this bit is high, the user must maintain the same logical
value to the other bits in this register to avoid any change in the device setting.
Table 5 - Internal Mode Selection Register (IMS) Bits
External Read/Write Address: 0001
H
Reset Value: 0000
H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000STIO_
PD_EN
0 BDL 0 0 BPD
2
BPD
1
BPD
0
MBPS
BDL STio0 - 15 Operation
0 normal operation:
STi0-15 are inputs
STio0-15 are outputs
1 bi-directional operation:
STi0-15 tied low internally
STio0-15 are bi-directional

ZL50017GAG2

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Digital Bus Switch ICs Pb Free Basic 1K DX
Lifecycle:
New from this manufacturer.
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