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ZL50017GAG2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51
ZL50017 Data Sheet
13
Zarlink Semiconductor Inc.
N4, P4, R4,
P5, N13,
P11, R14,
R15, M15,
L15, L13,
L14, E14,
D13, D15,
C15
6, 7, 9,
10, 51,
52, 53,
54, 70,
72, 73,
74, 115,
116, 117,
118
STio 0 - 15 Serial Output Streams 0 to 15 (5 V-Tolerant Slew-Rate-Limited
Three-state I/Os with Enabled Internal Pull-downs)
The data rate of all the output streams are programmed through
the “Data Rate Selection Register” on page 31. In the 2.048 Mbps
mode, these pins output serial TDM data streams at 2.048 Mbps
with 32 channels per frame. In the 4.096 Mbps mode, these pins
output serial TDM data streams at 4.096 Mbps with 64 channels
per frame. In the 8.192 Mbps mode, these pins output serial TDM
data streams at 8.192 Mbps with 128 channels per frame. In the
16.384 Mbps mode, these pins output serial TDM data streams at
16.384 Mbps with 256 channels per frame.These output streams
can be used as bi-directionals by programming BDL (bit 6) of
Internal Mode Selection (IMS) register.
B15 141 ODE Output Drive Enable (5 V-Tolerant Input with Internal Pull-up)
This is the output enable control for STio0 - 15. When it is high,
STio0 - 15 are enabled. When it is low, STio0 - 15 are tristated.
M4, N6, R6,
P7, R7, N7,
M8, N8, P8,
R8, M9, N9,
R9, N10, P9,
R10
16, 18,
20, 22,
23, 24,
25, 26,
27, 28,
30, 32,
34, 36,
37, 38
D0 - 15 Data Bus 0 to 15 (5 V-Tolerant Slew-Rate-Limited Three-state
I/Os)
These pins form the 16-bit data bus of the microprocessor port.
N12 44 DTA
_RDY Data Transfer Acknowledgment_Ready (5 V-Tolerant
Three-state Output)
This active low output indicates that a data bus transfer is
complete for the Motorola interface. For the Intel interface, it
indicates a transfer is completed when this pin goes from low to
high. An external pull-up resistor MUST hold this pin at HIGH level
for the Motorola mode. An external pull-down resistor MUST hold
this pin at LOW level for the Intel mode.
R11 40 CS
Chip Select (5 V-Tolerant Input)
Active low input used by the Motorola or Intel microprocessor to
enable the microprocessor port access.
N11 39 R/W
_WR Read/Write_Write (5 V-Tolerant Input)
This input controls the direction of the data bus lines (D0 - 15)
during a microprocessor access. For the Motorola interface, this
pin is set high and low for the read and write access respectively.
For the Intel interface, a write access is indicated when this pin
goes low.
R12 42 DS
_RD Data Strobe_Read (5 V-Tolerant Input)
This active low input works in conjunction with CS
to enable the
microprocessor port read and write operations for the Motorola
interface. A read access is indicated when it goes low for the Intel
interface.
PBGA Pin
Number
LQFP Pin
Number
Pin Name Description
ZL50017 Data Sheet
14
Zarlink Semiconductor Inc.
3.0 Device Overview
The device has sixteen ST-BUS/GCI-Bus inputs (STi0 - 15) and sixteen ST-BUS/GCI-Bus outputs (STio0 - 15).
STio0 - 15 can also be configured as bi-directional pins, in which case STi0 - 15 will be ignored. It is a non-blocking
digital switch with 1024 64 kbps channels. The ST-BUS/GCI-Bus inputs and outputs accept serial input data
streams with data rates of 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps.
By using Zarlink’s message mode capability, microprocessor data stored in the connection memory can be
broadcast to the output streams on a per-channel basis. This feature is useful for transferring control and status
information for external circuits or other ST-BUS/GCI-Bus devices.
The device uses the ST-BUS/GCI-Bus input frame pulse (FPi) and the ST-BUS/GCI-Bus input clock (CKi) to define
the input frame boundary and timing for sampling the ST-BUS/GCI-Bus input streams with various data rates. The
output data streams will be driven by and have their timing defined by FPi and CKi. A Motorola or Intel compatible
non-multiplexed microprocessor port allows users to program the device to operate in various modes under
different switching configurations. Users can use the microprocessor port to perform internal register and memory
read and write operations. The microprocessor port has a 16-bit data bus, a 14-bit address bus and six control
signals (MOT_INTEL
, CS, DS_RD, R/W_WR and DTA_RDY).
The device supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.
4.0 Data Rates and Timing
The ZL50017 has 16 serial data inputs and 16 serial data outputs. All streams are programmed to operate at
2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps. Depending on the data rate there will be 32 channels, 64
channels, 128 channels or 256 channels, respectively, during a 125 µs frame.
K13, K15,
K14, J11,
J12, J13,
J15, H11,
J14, H12,
H13, H15,
G12, G13
82, 84,
86, 87,
88, 89,
90, 91,
92, 93,
94, 96,
98, 99
A0 - 13 Address 0 to 13 (5 V-Tolerant Inputs)
These pins form the 14-bit address bus to the internal memories
and registers.
M13 41 MOT_INTEL
Motorola_Intel (5 V-Tolerant Input with Internal Pull-up)
This pin selects the Motorola or Intel microprocessor interface to
be connected to the device. When this pin is unconnected or
connected to high, Motorola interface is assumed. When this pin
is connected to ground, Intel interface should be used.
G2 211 RESET
Device Reset (5 V-Tolerant Input with Internal Pull-up)
This input (active LOW) puts the device in its reset state that
disables the STio0 - 15 drivers. It also preloads registers with
default values and clears all internal counters. To ensure proper
reset action, the reset pin must be low for longer than 1 µs. Upon
releasing the reset signal to the device, the first microprocessor
access cannot take place for at least 500 µs due to the time
required to stabilize the device from the power-down state. Refer
to Section Section 10.2 on page 25 for details.
PBGA Pin
Number
LQFP Pin
Number
Pin Name Description
ZL50017 Data Sheet
15
Zarlink Semiconductor Inc.
The output streams can be programmed to operate as bi-directional streams. By setting BDL (bit 6) in the Internal
Mode Selection (IMS) register, the input streams 0 - 15 (STi0 - 15) are internally tied low, and the output streams 0
- 15 (STio0 - 15) are set to operate in a bi-directional mode.The input data rate is set on a per-stream basis by
programming STIN[n]DR3 - 0 (bits 3 - 0) in the Stream Input Control Register 0 - 15 (SICR0 - 15). The output data
rate is set on a per-stream basis by programming STO[n]DR3 - 0 (bits 3 - 0) in the Stream Output Control Register
0 - 15 (SOCR0 - 15). The output data rates do not have to match or follow the input data rates. The maximum
number of channels switched is limited to 1024 channels. If all 16 input streams were operating at 8.192 Mbps (128
channels per stream), this would result in 2048 channels. Memory limitations prevent the device from operating at
this capacity. A maximum capacity of 1024 channels will occur if four streams are operating at 16.384 Mbps, eight
streams are operating at 8.192 Mbps or all sixteen streams are operating at 4.096 Mbps. With all streams operating
at 2.048 Mbps, the capacity will be reduced to 512 channels. It should be noted that only full streams can be
enabled, the device does not allow partial streams configuration (i.e., cannot have all the streams operating at
16.384 Mbps but only access the half the channels).
4.1 Input Clock (CKi) and Input Frame Pulse (FPi) Timing
The frequency of the input clock (CKi) for the ZL50017 must be at least twice the input/output data rate. For
example, if the input/output data rate is 8.192 Mbps, the input clock, CKi, must be 16.384 MHz. Following the
example above, if the input/output data rate is 4.096 Mbps, the input clock, CKi, must be 8.192 MHz.The only
exception to this is for 16.384 Mbps input/output data. In this case, the input clock, CKi, is equal to the data rate.
The input frame pulse, FPi, must always follow CKi. CKIN1 - 0 (bits 6 - 5) in the Control Register (CR) are used to
program the width of the input frame pulse and the frequency of the input clock supplied to the device.
The ZL50017 accepts positive and negative ST-BUS/GCI-Bus input clock and input frame pulse formats via the
programming of CKINP (bit 8) and FPINP (bit 7) in the Control Register (CR). By default, the device accepts the
negative input clock format and ST-BUS format frame pulses. However, the switch can also accept a positive-going
clock format by programming CKINP (bit 8) in the Control Register (CR). A GCI-Bus format frame pulse can be
used by programming FPINPOS (bit 9) and FPINP (bit 7) in the Control Register (CR).
Figure 4 - Input Timing when CKIN1 - 0 bits = “10” in the CR
FPi (244 ns)
FPINP = 0
FPINPOS = 0
FPi (244 ns)
FPINP = 1
FPINPOS = 0
FPi (244 ns)
FPINP = 0
FPINPOS = 1
FPi (244 ns)
FPINP = 1
FPINPOS = 1
CKi
(4.096 MHz)
CKINP = 0
CKi
(4.096 MHz)
CKINP = 1
76 100 7
STi
(2.048 Mbps)
Channel 0 Channel 31
ST-BUS
GCI-Bus
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51

ZL50017GAG2

Mfr. #:
Buy ZL50017GAG2
Manufacturer:
Microchip / Microsemi
Description:
Digital Bus Switch ICs Pb Free Basic 1K DX
Lifecycle:
New from this manufacturer.
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