ZL50017 Data Sheet
20
Zarlink Semiconductor Inc.
The input delay is controlled by STIN[n]BD2-0 (bits 8 - 6) to control the bit shift and STIN[n]SMP1 - 0 (bits 5 - 4) to
control the sampling point in the Stream Input Control Register 0 - 15 (SICR0 - 15).
Figure 9 - Input Bit Delay and Factional Sampling Point
5.3 Output Advancement Programming
This feature is used to advance the output data of individual output streams with respect to the input frame
boundary. Each output stream has its own bit advancement value which can be programmed in the Stream Output
Control Register 0 - 15 (SOCR0 - 15).
By default, all output streams have zero bit advancement such that bit 7 is the first bit that appears after the input
frame boundary (assuming ST-BUS formatting). The output advancement is enabled by STO[n]AD 2 - 0 (bits 6 - 4)
of the Stream Output Control Register 0 - 15 (SOCR0 - 15) as described in Table 10 on page 33. The output bit
advancement can vary from 0 to 7 bits.
Nominal Channel n+1 Boundary
7 6 5 4 3 2 1 0 70
000 01
000 10
000 00 (Default)
000 11
001 01
001 10
001 00
001 11
010 01
010 10
010 00
010 11
011 01
011 10
011 00
011 11
111 00
111 10
111 01
110 11
110 00
110 10
110 01
101 11
101 00
101 10
101 01
100 11
100 00
100 10
100 01
111 11
The first 3 bits represent STIN[n]BD2 - 0 for setting the bit delay.
The second set of 2 bits represent STIN[n]SMP1 - 0 for setting the sampling point offset.
STi[n]
Nominal Channel n Boundary
Example: With a setting of 011 10 the offset will be 3 bits at a 1/2 sampling point.
Note: Italic settings can be used in 16 Mbps mode (1/2 and 4/4 sampling point).
