ZL50017 Data Sheet
25
Zarlink Semiconductor Inc.
10.0 Device Reset and Initialization
The RESET pin is used to reset the ZL50017. When this pin is low, the following functions are performed:
• synchronously puts the microprocessor port in a reset state
• tristates the STio0 - 15 outputs
• preloads all internal registers with their default values (refer to the individual registers for default values)
• clears all internal counters
10.1 Power-up Sequence
The recommended power-up sequence is for the V
DD_IO
supply (normally +3.3 V) to be established before the
power-up of the V
DD_CORE
supply (normally +1.8 V). The V
DD_CORE
supply may be powered up at the same time
as V
DD_IO
, but should not “lead” the V
DD_IO
supply by more than 0.3 V.
10.2 Device Initialization on Reset
Upon power up, the ZL50017 should be initialized as follows:
• Set the ODE pin to low to disable the STio0 - 15 outputs
• Set the TRST
pin to low to disable the JTAG TAP controller
• Reset the device by pulsing the RESET
pin to zero for longer than 1 µs
• After releasing the RESET
pin from low to high, wait for a certain period of time (see Note below) for the
device to stabilize from the power down state before the first microprocessor port access can occur
• Wait at least 500 µs prior to the next microport access (see Note below)
• Use the block programming mode to initialize the connection memory
• Release the ODE pin from low to high after the connection memory is programmed
Note: If CKi is 16.384 MHz, the waiting time is 500 µs; if CKi is 8.192 MHz, the waiting time is 1 ms; if CKi is
4.096 MHz, the waiting time is 2 ms.
10.3 Software Reset
In addition to the hardware reset from the RESET pin, the device can also be reset by using software reset
SRSTSW (bit 1) in the Software Reset Register (SRR).
11.0 JTAG Port
The JTAG test port is implemented to meet the mandatory requirements of the IEEE-1149.1 (JTAG) standard. The
operation of the boundary-scan circuitry is controlled by an external Test Access Port (TAP) Controller.
11.1 Test Access Port (TAP)
The Test Access Port (TAP) accesses the ZL50017 test functions. It consists of three input pins and one output pin
as follows:
• Test Clock Input (TCK) - TCK provides the clock for the test logic. TCK does not interfere with any on-chip
clock and thus remains independent in the functional mode. TCK permits shifting of test data into or out of
the Boundary-Scan register cells concurrently with the operation of the device and without interfering with
the on-chip logic.
