ZL50017 Data Sheet
46
Zarlink Semiconductor Inc.
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc-
tion testing.
Note 1: High impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel the time taken to
discharge C
L
.
AC Electrical Characteristics
†
- ST-BUS/GCI-Bus Input Timing
Characteristic Sym. Min. Typ.
‡
Max. Units Test Conditions
1 STi Setup Time
2.048 Mbps
4.096 Mbps
8.192 Mbps
16.384 Mbps
t
SIS2
t
SIS4
t
SIS8
t
SIS16
5
5
5
5
ns
ns
ns
ns
2STi Hold Time
2.048 Mbps
4.096 Mbps
8.192 Mbps
16.384 Mbps
t
SIH2
t
SIH4
t
SIH8
t
SIH16
8
8
8
8
ns
ns
ns
ns
3 STio Delay - Active to Active
@2.048 Mbps
@4.096 Mbps
@8.192 Mbps
@16.384 Mbps
t
SOD2
t
SOD4
t
SOD8
t
SOD16
-6
-6
-6
-6
0
0
0
0
ns
ns
ns
ns
C
L
= 30 pF
4 STio Delay - Active to High-Z
STio Delay - High-Z to Active
2.048 Mbps
4.096 Mbps
8.192 Mbps
16.384 Mbps
t
DZ
t
ZD
-8
-8
-8
-8
0
0
0
0
ns
ns
ns
ns
R
L
= 1 k,
C
L
= 30 pF,
See Note 1.
5 Output Drive Enable (ODE)
Delay
- High-Z to
Active
t
ZD_OD
E
260 ns
6 Output Drive Enable (ODE)
Delay
- Active to High-Z
t
DZ_OD
E
260
ns
