ZL50017 Data Sheet
22
Zarlink Semiconductor Inc.
6.0 Data Delay Through the Switching Paths
The switching of information from the input serial streams to the output serial streams results in a throughput delay.
The device can be programmed to perform timeslot interchange functions with different throughput delay
capabilities on a per-channel basis. For voice applications, select variable throughput delay to ensure minimum
delay between input and output data. In wideband data applications, select constant delay to maintain the frame
integrity of the information through the switch. The delay through the device varies according to the type of
throughput delay selected by the V/C
(bit 14) in the Connection Memory Low when CMM = 0.
6.1 Variable Delay Mode
Variable delay mode causes the output channel to be transmitted as soon as possible. This is a useful mode for
voice applications where the minimum throughput delay is more important than frame integrity. The delay through
the switch can vary from 7 channels to 1 frame + 7 channels. To set the device into variable delay mode, VAREN
(bit 4) in the Control Register (CR) must be set before V/C
(bit 14) in the Connection Memory Low when CMM = 0.
If the VAREN bit is not set and the device is programmed for variable delay mode, the information read on the
output stream will not be valid.
In variable delay mode, the delay depends on the combination of the source and destination channels of the input
and output streams.
For example, if Stream 4 Channel 2 is switched to Stream 5 Channel 9 with variable delay, the data will be output in
the same 125 µs frame. Contrarily, if Stream 6 Channel 1 is switched to Stream 9 Channel 3, the information will
appear in the following frame.
Figure 12 - Data Throughput Delay for Variable Delay
m = input channel number
n = output channel number
n-m <= 0 0 < n-m < 7 n-m = 7 n-m > 7
STio < STi STio >= STi
T = Delay between input and output 1 frame - (m-n) 1 frame + (n-m) n-m
Table 1 - Delay for Variable Delay Mode
L-2 L-1 CH0 CH1 CH2 CH3 L-2 L-1 CH0 CH1 CH2 CH3
L-2 L-1 CH0 CH1 CH2 CH3 L-2 L-1 CH0 CH1 CH2 CH3
L-2 L-1 CH0 CH1 CH2 CH3 L-2 L-1 CH0 CH1 CH2 CH3
L-2 L-1 CH0 CH1 CH2 CH3 L-2 L-1 CH0 CH1 CH2 CH3
CH4 CH5 CH6
CH4 CH5 CH6
CH4 CH5 CH6
CH4 CH5 CH6
CH7 CH8 CH9
CH7 CH8 CH9
CH7 CH8 CH9
CH7 CH8 CH9
STi4
CH2
STio5
CH9
STi6
CH1
STio9
CH3
Frame N
Frame N + 1
L = last channel = 31, 63, 127 or 255 for 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps respectively.
ZL50017 Data Sheet
23
Zarlink Semiconductor Inc.
6.2 Constant Delay Mode
In this mode, frame integrity is maintained in all switching configurations. The delay though the switch is 2 frames -
Input Channel + Output Channel. This can result in a minimum of 1 frame + 1 channel delay if the last channel on a
stream is switched to the first channel of a stream. The maximum delay is 3 frames - 1 channel. This occurs when
the first channel of a stream is switched to the last channel of a stream. The constant delay mode is available for all
output channels.
The data throughput delay is expressed as a function of ST-BUS/GCI-Bus frames, input channel number (m) and
output channel number (n). The data throughput delay (T) is:
T = 2 frames + (n - m)
The constant delay mode is controlled by V/C
(bit 14) in the Connection Memory Low when CMM = 0. When this bit
is set low, the channel is in constant delay mode. If VAREN (bit 4) in the Control Register (CR) is set (to enable
variable throughput delay on a chip-wide basis), the device can still be programmed to operate in constant delay
mode.
Figure 13 - Data Throughput Delay for Constant Delay
7.0 Connection Memory Description
The connection memory consists of two blocks, Connection Memory Low (CM_L). The CM_L is 16 bits wide and is
used for channel switching and other special modes. Each connection memory location of the CM_L or CM_H can
be read or written via the 16 bit microprocessor port within one microprocessor access cycle. See Table 11 on
page 34 for the address mapping of the connection memory. Any unused bits will be reset to zero on the 16-bit data
bus.
For the normal channel switching operation, CMM (bit 0) of the Connection Memory Low (CM_L) is programmed
low. SCA7 - 0 (bits 8 - 1) indicate the source (input) channel address and SSA4 - 0 (bits 13 - 9) indicate the source
(input) stream address. When CMM (bit 0) of the Connection Memory Low (CM_L) is programmed high, the
ZL50017 will operate in one of the special modes described in Table 13 on page 36. When the per-channel
message mode is enabled, MSG7 - 0 (bit 10 - 3) in the Connection Memory Low (CM_L) will be output via the serial
data stream as message output data.
L-2 L-1 CH0 CH1 CH2 CH3 L-2 L-1 CH0 CH1 CH2 CH3 L-2 L-1 CH0 CH1 CH2 CH3
L-2 L-1 CH0 CH1 CH2 CH3 L-2 L-1 CH0 CH1 CH2 CH3 L-2 L-1 CH0 CH1 CH2 CH3
L-2 L-1 CH0 CH1 CH2 CH3 L-2 L-1 CH0 CH1 CH2 CH3 L-2 L-1 CH0 CH1 CH2 CH3
L-2 L-1 CH0 CH1 CH2 CH3 L-2 L-1 CH0 CH1 CH2 CH3 L-2 L-1 CH0 CH1 CH2 CH3
STi
STio
STi
STio
L = last channel = 31, 63, 127 or 255 for 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps respectively.
Frame N
Frame N + 1
Frame N + 2
ZL50017 Data Sheet
24
Zarlink Semiconductor Inc.
8.0 Connection Memory Block Programming
This feature allows for fast initialization of the connection memory after power up.
8.1 Memory Block Programming Procedure
1. Set MBPE (bit 3) in the Control Register (CR) from low to high.
2. Configure BPD2 - 0 (bits 3 - 1) in the Internal Mode Selection (IMS) register to the desired values to be loaded
into CM_L.
3. Start the block programming by setting MBPS (bit 0) in the Internal Mode Selection Register (IMS) high. The val-
ues stored in BPD2 - 0 will be loaded into bits 2 - 0 of all CM_L positions. The remaining CM_L locations (bits 15
- 3).
The following tables show the resulting values that are in the CM_L and CM_H connection memory locations.
It takes at least two frame periods (250 µs) to complete a block program cycle.
MBPS (bit 0) in the Control Register (CR) will automatically reset to a low position after the block programming
process has completed.
MBPE (bit 3) in the Internal Mode Selection (IMS) register must be cleared from high to low to terminate the block
programming process. This is not an automatic action taken by the device and must be performed manually.
Note: Once the block program has been initiated, it can be terminated at any time prior to completion by setting
MBPS (bit 0) in the Control Register (CR) or MBPE (bit 3) in the Internal Mode Selection (IMS) register to low.
9.0 Microprocessor Port
The device provides access to the internal registers, connection memories and data memories via the
microprocessor port. The microprocessor port is capable of supporting both Motorola and Intel non-multiplexed
microprocessors. The microprocessor port consists of a 16-bit parallel data bus (D15 - 0), 14 bit address bus (A13 -
0) and six control signals (MOT_INTEL
, CS, DS_RD, R/W_WR and DTA_RDY).
The data memory can only be read from the microprocessor port. For a data memory read operation, D7 - 0 will be
used and D15 - 8 will output zeros.
For a CM_L read or write operation, all bits (D15 - 0) of the data bus will be used. For a CM_H write operation, D4 -
0 of the data bus must be configured and D15 - 5 are ignored. D15 - 5 must be driven either high or low. For a
CM_H read operation, D4 - 0 will be used and D15 - 5 will output zeros.
Refer to Figure 15 on page 39, Figure 16 on page 40, Figure 17 on page 41 and Figure 18 on page 42 for the
microprocessor timing.
Bit1514131211109876543 2 1 0
Value0000000000000BPD2BPD1BPD0
Table 2 - Connection Memory Low After Block Programming

ZL50017GAG2

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Digital Bus Switch ICs Pb Free Basic 1K DX
Lifecycle:
New from this manufacturer.
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