ZL50017 Data Sheet
17
Zarlink Semiconductor Inc.
4.2 ST-BUS and GCI-Bus Timing
The ZL50017 is capable of operating using either the ST-BUS or GCI-Bus standards. By default, the ZL50017 is
configured for ST-BUS input and output timing. To set the input timing to conform to the GCI-Bus standard,
FPINPOS (bit 9) and FPINP (bit 7) in the Control Register (CR) must be set.
5.0 Data Input Delay and Data Output Advancement
Various registers are provided to adjust the input delay and output advancement for each input and output data
stream. The input bit delay and output bit advancement can vary from 0 to 7 bits for each individual stream.
If input delay of less than a bit is desired, different sampling points can be used to handle the adjustments. The
sampling point can vary from 1/4 to 4/4 with a 1/4-bit increment for all input streams. By default, the sampling point
is set to the 3/4-bit location.
The fractional output bit advancement can vary from 0 to 3/4 bits, again with a 1/4 bit increment. By default, there is
0 output bit advancement.
Although input delay or output advancement features are available on streams which are operating in bi-directional
mode it is not recommended, as it can easily cause bus contention. If users require this function, special attention
must be given to the timing to ensure contention is minimized.
