Operating Features
Page Programming
To program one data byte, two commands are required: WRITE ENABLE, which is one
byte, and a PAGE PROGRAM sequence, which is four bytes plus data. This is followed by
the internal PROGRAM cycle of duration
t
PP. To spread this overhead, the PAGE PRO-
GRAM command allows up to 256 bytes to be programmed at a time (changing bits
from 1 to 0), provided they lie in consecutive addresses on the same page of memory. To
optimize timings, it is recommended to use the PAGE PROGRAM command to program
all consecutive targeted bytes in a single sequence than to use several PAGE PROGRAM
sequences with each containing only a few bytes.
Sector Erase, Bulk Erase
The PAGE PROGRAM command allows bits to be reset from 1 to 0. Before this can be
applied, the bytes of memory need to have been erased to all 1s (FFh). This can be ach-
ieved a sector at a time using the SECTOR ERASE command, or throughout the entire
memory using the BULK ERASE command. This starts an internal ERASE cycle of dura-
tion
t
SSE,
t
SE, or
t
BE. The ERASE command must be preceded by a WRITE ENABLE
command.
Polling during a Write, Program, or Erase Cycle
An improvement in the time to complete the following commands can be achieved by
not waiting for the worst case delay (
t
W,
t
PP,
t
SE, or
t
BE).
WRITE STATUS REGISTER
PROGRAM
ERASE (SECTOR ERASE, BULK ERASE)
The write in progress (WIP) bit is provided in the status register so that the application
program can monitor this bit in the status register, polling it to establish when the pre-
vious WRITE cycle, PROGRAM cycle, or ERASE cycle is complete.
Fast Program/Erase Mode
The fast program/erase mode is used to speed up programming/erasing. The device en-
ters this mode during the PAGE PROGRAM, SECTOR ERASE, or BULK ERASE operations
whenever a voltage equal to V
PPH
is applied to the W#/V
PP
pin.
The use of this mode requires specific operating conditions in addition to the normal
ones (V
CC
must be within the normal operating range):
The voltage applied to the W#/V
PP
pin must be equal to V
PPH
Ambient temperature, T
A
must be 25 °C ±10 °C
The cumulated time during which W#/V
PP
is at V
PPH
should be less than 80 hours
Active Power and Standby Power
When chip select (S#) is LOW, the device is selected, and in the active power mode.
When S# is HIGH, the device is deselected, but could remain in the active power mode
until all internal cycles have completed (PROGRAM, ERASE, WRITE STATUS REGIS-
M25P128 Serial Flash Embedded Memory
Operating Features
CCMTD-1718347970-10412
m25p_128.pdf - Rev. A 11/16 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
TER). The device then goes in to the standby power mode. The device consumption
drops to I
CC1
.
Status Register
The status register contains a number of status and control bits that can be read or set
(as appropriate) by specific commands. For a detailed description of the status register
bits, see READ STATUS REGISTER section.
Data Protection by Protocol
Nonvolatile memory is used in environments that can include excessive noise. The fol-
lowing capabilities help protect data in these noisy environments.
Power on reset and an internal timer (
t
PUW) can provide protection against inadvertent
changes while the power supply is outside the operating specification.
WRITE, PROGRAM, and WRITE STATUS REGISTER commands are checked before they
are accepted for execution to ensure they consist of a number of clock pulses that is a
multiple of eight.
All commands that modify data must be preceded by a WRITE ENABLE command to set
the write enable latch (WEL) bit.
Software Data Protection
Memory can be configured as read-only using the block protect bits (BP2, BP1, BP0) as
shown in the Protected Area Sizes table.
Hardware Data Protection
Hardware data protection is implemented using the write protect signal applied on the
W# pin. This freezes the status register in a read-only mode. In this mode, the block pro-
tect (BP) bits and the status register write disable bit (SRWD) are protected.
Table 2: Protected Area Sizes
Status Register Content Memory Content
BP Bit 2 BP Bit 1 BP Bit 0 Protected Area Unprotected Area
0 0 0 none All sectors (sectors 0 to 63)
0 0 1 Upper 64th (sector 63, 2Mb) Lower 63/64ths (sectors 0 to 62)
0 1 0 Upper 32nd (sectors 62 and 63, 4Mb) Lower 31/32nds (sectors 0 to 61)
0 1 1 Upper 16th (sectors 60 and 63, 8Mb) Lower 15/16ths (sectors 0 to 59)
1 0 0 Upper 8th (sectors 56 to 63, 16Mb) Lower 7/8ths (sectors 0 to 55)
1 0 1 Upper 4th (sectors 48 to 63, 32Mb) Lower 3/4ths (sectors 0 to 47)
1 1 0 Upper half (sectors 32 to 63, 64Mb) Lower half (sectors 0 to 31)
1 1 1 All sectors (sectors 0 to 63, 128Mb) none
Note:
1. 0 0 0 = unprotected area (sectors): The device is ready to accept a BULK ERASE command
only if all block protect bits (BP2, BP1, BP0) are 0.
M25P128 Serial Flash Embedded Memory
Operating Features
CCMTD-1718347970-10412
m25p_128.pdf - Rev. A 11/16 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
Hold Condition
The HOLD# signal is used to pause any serial communications with the device without
resetting the clocking sequence. However, taking this signal LOW does not terminate
any WRITE STATUS REGISTER, PROGRAM, or ERASE cycle that is currently in progress.
To enter the hold condition, the device must be selected, with S# LOW. The hold condi-
tion starts on the falling edge of the HOLD# signal, if this coincides with serial clock (C)
being LOW. The hold condition ends on the rising edge of the HOLD# signal, if this co-
incides with C being LOW. If the falling edge does not coincide with C being LOW, the
hold condition starts after C next goes LOW. Similarly, if the rising edge does not coin-
cide with C being LOW, the hold condition ends after C next goes LOW.
During the hold condition, DQ1 is HIGH impedance while DQ0 and C are "Don’t Care."
Typically, the device remains selected with S# driven LOW for the duration of the hold
condition. This ensures that the state of the internal logic remains unchanged from the
moment of entering the hold condition. If S# goes HIGH while the device is in the hold
condition, the internal logic of the device is reset. To restart communication with the
device, it is necessary to drive HOLD# HIGH, and then to drive S# LOW. This prevents
the device from going back to the hold condition.
Figure 6: Hold Condition Activation
HOLD#
C
HOLD condition (standard use)
HOLD condition (nonstandard use)
M25P128 Serial Flash Embedded Memory
Operating Features
CCMTD-1718347970-10412
m25p_128.pdf - Rev. A 11/16 EN
12
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.

M25P128-VME6GB

Mfr. #:
Manufacturer:
Micron
Description:
IC FLASH 128M SPI 54MHZ 8VDFPN
Lifecycle:
New from this manufacturer.
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