Power-Up/Down and Supply Line Decoupling
At power-up and power-down, the device must not be selected; that is, chip select (S#)
must follow the voltage applied on V
CC
until V
CC
reaches the correct value:
• V
CC,min
at power-up, and then for a further delay of
t
VSL
• V
SS
at power-down
A safe configuration is provided in the SPI Modes section.
To avoid data corruption and inadvertent WRITE operations during power-up, a power-
on-reset (POR) circuit is included. The logic inside the device is held reset while V
CC
is
less than the POR threshold voltage, V
WI
– all operations are disabled, and the device
does not respond to any instruction. Moreover, the device ignores the following instruc-
tions until a time delay of
t
PUW has elapsed after the moment that V
CC
rises above the
V
WI
threshold:
• WRITE ENABLE
• PAGE PROGRAM
• SECTOR ERASE
• BULK ERASE
• WRITE STATUS REGISTER
However, the correct operation of the device is not guaranteed if, by this time, V
CC
is still
below V
CC.min
. No WRITE STATUS REGISTER, PROGRAM, or ERASE instruction should
be sent until:
•
t
PUW after V
CC
has passed the V
WI
threshold
•
t
VSL after V
CC
has passed the V
CC,min
level
If the time,
t
VSL, has elapsed, after V
CC
rises above V
CC,min
, the device can be selected
for READ instructions even if the
t
PUW delay has not yet fully elapsed.
V
PPH
must be applied only when V
CC
is stable and in the V
CC,min
to V
CC,max
voltage
range.
M25P128 Serial Flash Embedded Memory
Power-Up/Down and Supply Line Decoupling
CCMTD-1718347970-10412
m25p_128.pdf - Rev. A 11/16 EN
29
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
