Signal Descriptions
Table 1: Signal Descriptions
Signal Type Description
DQ1 Output Serial data: The DQ1 output signal is used to transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock (C).
DQ0 Input Serial data: The DQ0 input signal is used to transfer data serially into the device. It
receives commands, addresses, and the data to be programmed. Values are latched on
the rising edge of the serial clock (C).
C Input Clock: The C input signal provides the timing of the serial interface. Commands, ad-
dresses, or data present at serial data input (DQ0) is latched on the rising edge of the
serial clock (C). Data on DQ1 changes after the falling edge of C.
S# Input Chip select: When the S# input signal is HIGH, the device is deselected and DQ1 is at
high impedance. Unless an internal PROGRAM, ERASE, or WRITE STATUS REGISTER cy-
cle is in progress, the device will be in the standby power mode. Driving S# LOW ena-
bles the device, placing it in the active power mode. After power-up, a falling edge on
S# is required prior to the start of any command.
HOLD# Input Hold: The HOLD# signal is used to pause any serial communications with the device
without deselecting the device. During the hold condition, DQ1 is High-Z. DQ0 and C
are "Don’t Care." To start the hold condition, the device must be selected, with S#
driven LOW.
W#/V
PP
Input Write protect: The W#/V
PP
signal is both a control input and a power supply pin. The
two functions are selected by the voltage range applied to the pin. If the W#/V
PP
input
is kept in a low voltage range (0 V to V
CC
) the pin is seen as a control input. The W#
input signal is used to freeze the size of the area of memory that is protected against
program or erase commands as specified by the values in BP2, BP1, and BP0 bits of the
Status Register. V
PP
acts as an additional power supply if it is in the range of V
PPH
, as
defined in the AC Measurement Conditions table. Avoid applying V
PPH
to the W#/V
PP
pin during a BULK ERASE operation.
V
CC
Power Device core power supply: Source voltage.
V
SS
Ground Ground: Reference for the V
CC
supply voltage.
DNU Do not use.
M25P128 Serial Flash Embedded Memory
Signal Descriptions
CCMTD-1718347970-10412
m25p_128.pdf - Rev. A 11/16 EN
7
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
SPI Modes
These devices can be driven by a microcontroller with its serial peripheral interface
(SPI) running in either of the following two SPI modes:
CPOL = 0, CPHA = 0
CPOL = 1, CPHA = 1
For these two modes, input data is latched in on the rising edge of serial clock (C), and
output data is available from the falling edge of C.
The difference between the two modes is the clock polarity when the bus master is in
standby mode and not transferring data:
C remains at 0 for (CPOL = 0, CPHA = 0)
C remains at 1 for (CPOL = 1, CPHA = 1)
Figure 4: SPI Modes Supported
C
MSB
CPHA
DQ0
0
1
CPOL
0
1
DQ1
C
MSB
Because only one device is selected at a time, only one device drives the serial data out-
put (DQ1) line at a time, while the other devices are High-Z. An example of three devi-
ces connected to an MCU on an SPI bus is shown here.
M25P128 Serial Flash Embedded Memory
SPI Modes
CCMTD-1718347970-10412
m25p_128.pdf - Rev. A 11/16 EN
8
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
Figure 5: Bus Master and Memory Devices on the SPI Bus
SPI Bus Master
SPI memory
device
SDO
SDI
SCK
C
DQ1 DQ0
S#
SPI memory
device
C
DQ1 DQ0
S#
SPI memory
device
C
DQ1 DQ0
S#
CS3 CS2 CS1
SPI interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
W#
HOLD#
HOLD#
W#
HOLD#
R R R
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
R
W#
Notes:
1. WRITE PROTECT (W#) and HOLD# should be driven HIGH or LOW as appropriate.
2. Resistors (R) ensure that the memory device is not selected if the bus master leaves the
S# line High-Z.
3. The bus master may enter a state where all I/O are High-Z at the same time; for exam-
ple, when the bus master is reset. Therefore, C must be connected to an external pull-
down resistor so that when all I/O are High-Z, S# is pulled HIGH while C is pulled LOW.
This ensures that S# and C do not go HIGH at the same time and that the
t
SHCH require-
ment is met.
4. The typical value of R is 100kΩ, assuming that the time constant R × C
p
(C
p
= parasitic
capacitance of the bus line) is shorter than the time during which the bus master leaves
the SPI bus High-Z.
5. Example: Given that C
p
= 50pF (R × C
p
= 5μs), the application must ensure that the bus
master never leaves the SPI bus High-Z for a time period shorter than 5μs.
M25P128 Serial Flash Embedded Memory
SPI Modes
CCMTD-1718347970-10412
m25p_128.pdf - Rev. A 11/16 EN
9
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.

M25P128-VME6GB

Mfr. #:
Manufacturer:
Micron
Description:
IC FLASH 128M SPI 54MHZ 8VDFPN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union