OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

M25P128-VME6GB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42
WRITE STATUS REGISTER
The WRITE STATUS REGISTER command allows new values to be written to the status
register. Before the WRITE STATUS REGISTER command can be accepted, a WRITE EN-
ABLE command must have been executed previously. After the WRITE ENABLE com-
mand has been decoded and executed, the device sets the write enable latch (WEL) bit.
The WRITE STATUS REGISTER command is entered by driving chip select (S#) LOW,
followed by the command code and the data byte on serial data input (DQ0). The
WRITE STATUS REGISTER command has no effect on b6, b5, b4, b1, and b0 of the sta-
tus register. The status register b6, b5, and b4 are always read as "0". S# must be driven
HIGH after the eighth bit of the data byte has been latched in. If not, the WRITE STATUS
REGISTER command is not executed.
Figure 13: WRITE STATUS REGISTER Command Sequence
7 8 9 10 11 12 13
14
15
0
C
MSB
DQ0
LSB
Command
MSB
LSB
D
IN
D
IN
D
IN
D
IN
D
IN
D
IN
D
IN
D
IN
D
IN
As soon as S# is driven HIGH, the self-timed WRITE STATUS REGISTER cycle is initi-
ated; its duration is
t
W. While the WRITE STATUS REGISTER cycle is in progress, the sta-
tus register may still be read to check the value of the write in progress (WIP) bit. The
WIP bit is 1 during the self-timed WRITE STATUS REGISTER cycle, and is 0 when the
cycle is completed. Also, when the cycle is completed, the WEL bit is reset.
The WRITE STATUS REGISTER command allows the user to change the values of the
block protect bits (BP2, BP1, BP0). Setting these bit values defines the size of the area
that is to be treated as read-only, as defined in the Protected Area Sizes table.
The WRITE STATUS REGISTER command also allows the user to set and reset the status
register write disable (SRWD) bit in accordance with the write protect (W#/V
PP
) signal.
The SRWD bit and the W#/V
PP
signal allow the device to be put in the hardware protec-
ted (HPM) mode. The WRITE STATUS REGISTER command is not executed once the
HPM is entered. The options for enabling the status register protection modes are sum-
marized here.
M25P128 Serial Flash Embedded Memory
WRITE STATUS REGISTER
CCMTD-1718347970-10412
m25p_128.pdf - Rev. A 11/16 EN
22
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
Table 6: Status Register Protection Modes
W#/V
PP
Signal
SRWD
Bit
Protection
Mode (PM)
Status Register
Write Protection
Memory Content
Notes
Protected
Area
Unprotected
Area
1 0 Software
protected mode
(SPM)
Software protection Commands not
accepted
Commands
accepted
1, 2, 3
0 0
1 1
0 1 Hardware
protected mode
(HPM)
Hardware protection Commands not
accepted
Commands
accepted
3, 4, 5,
Notes:
1. Software protection: status register is writable (SRWD, BP2, BP1, and BP0 bit values can
be changed) if the WRITE ENABLE command has set the WEL bit.
2. PAGE PROGRAM, SECTOR ERASE, and BULK ERASE commands are not accepted.
3. PAGE PROGRAM and SECTOR ERASE commands can be accepted.
4. Hardware protection: status register is not writable (SRWD, BP2, BP1, and BP0 bit values
cannot be changed).
5. PAGE PROGRAM, SECTOR ERASE, and BULK ERASE commands are not accepted.
When the SRWD bit of the status register is 0 (its initial delivery state), it is possible to
write to the status register provided that the WEL bit has been set previously by a WRITE
ENABLE command, regardless of whether the W#/V
PP
signal is driven HIGH or LOW.
When the status register SRWD bit is set to 1, two cases need to be considered depend-
ing on the state of the W#/V
PP
signal:
• If the W#/V
PP
signal is driven HIGH, it is possible to write to the status register provi-
ded that the WEL bit has been set previously by a WRITE ENABLE command.
• If the W#/V
PP
signal is driven LOW, it is not possible to write to the status register even
if the WEL bit has been set previously by a WRITE ENABLE command. Therefore, at-
tempts to write to the status register are rejected, and are not accepted for execution.
The result is that all the data bytes in the memory area that have been put in SPM by
the status register block protect bits (BP2, BP1, BP0) are also hardware protected
against data modification.
Regardless of the order of the two events, the HPM can be entered in either of the fol-
lowing ways:
• Setting the status register SRWD bit after driving the W#/V
PP
signal LOW
• Driving the W#/V
PP
signal LOW after setting the status register SRWD bit.
The only way to exit the HPM is to pull the W#/V
PP
signal HIGH. If the W#/V
PP
signal is
permanently tied HIGH, the HPM can never be activated. In this case, only the SPM is
available, using the status register block protect bits (BP2, BP1, BP0).
M25P128 Serial Flash Embedded Memory
WRITE STATUS REGISTER
CCMTD-1718347970-10412
m25p_128.pdf - Rev. A 11/16 EN
23
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
READ DATA BYTES
The device is first selected by driving chip select (S#) LOW. The command code for
READ DATA BYTES is followed by a 3-byte address (A23-A0), each bit being latched-in
during the rising edge of serial clock (C). Then the memory contents at that address is
shifted out on serial data output (DQ1), each bit being shifted out at a maximum fre-
quency
f
R during the falling edge of C.
The first byte addressed can be at any location. The address is automatically incremen-
ted to the next higher address after each byte of data is shifted out. Therefore, the entire
memory can be read with a single READ DATA BYTES command. When the highest ad-
dress is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The READ DATA BYTES command is terminated by driving S# HIGH. S# can be driven
HIGH at any time during data output. Any READ DATA BYTES command issued while
an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without any effect on
the cycle that is in progress.
Figure 14: READ DATA BYTES Command Sequence
Don’t Care
MSB
DQ[0]
LSB
Command
A[MAX]
A[MIN]
7 8 C
x
0
C
High-Z
DQ1
MSB
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
LSB
D
OUT
D
OUT
D
OUT
D
OUT
Note:
1. Cx = 7 + (A[MAX] + 1).
M25P128 Serial Flash Embedded Memory
READ DATA BYTES
CCMTD-1718347970-10412
m25p_128.pdf - Rev. A 11/16 EN
24
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42

M25P128-VME6GB

Mfr. #:
Buy M25P128-VME6GB
Manufacturer:
Micron
Description:
IC FLASH 128M SPI 54MHZ 8VDFPN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet