READ DATA BYTES at HIGHER SPEED
The device is first selected by driving chip select (S#) LOW. The command code for the
READ DATA BYTES at HIGHER SPEED command is followed by a 3-byte address (A23-
A0) and a dummy byte, each bit being latched-in during the rising edge of serial clock
(C). Then the memory contents at that address are shifted out on serial data output
(DQ1) at a maximum frequency
f
C, during the falling edge of C.
The first byte addressed can be at any location. The address is automatically incremen-
ted to the next higher address after each byte of data is shifted out. Therefore, the entire
memory can be read with a single READ DATA BYTES at HIGHER SPEED command.
When the highest address is reached, the address counter rolls over to 000000h, allow-
ing the read sequence to be continued indefinitely.
The READ DATA BYTES at HIGHER SPEED command is terminated by driving S# HIGH.
S# can be driven HIGH at any time during data output. Any READ DATA BYTES at
HIGHER SPEED command issued while an ERASE, PROGRAM, or WRITE cycle is in
progress is rejected without any effect on the cycle that is in progress.
Figure 15: READ DATA BYTES at HIGHER SPEED Command Sequence
7 8 C
x
0
C
MSB
DQ0
LSB
Command
A[MAX]
A[MIN]
MSB
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
LSB
D
OUT
D
OUT
D
OUT
D
OUT
Dummy cycles
DQ1
High-Z
Don’t Care
Note:
1. Cx = 7 + (A[MAX] + 1).
M25P128 Serial Flash Embedded Memory
READ DATA BYTES at HIGHER SPEED
CCMTD-1718347970-10412
m25p_128.pdf - Rev. A 11/16 EN
25
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
PAGE PROGRAM
The PAGE PROGRAM command allows bytes in the memory to be programmed, which
means the bits are changed from 1 to 0. Before a PAGE PROGRAM command can be ac-
cepted a WRITE ENABLE command must be executed. After the WRITE ENABLE com-
mand has been decoded, the device sets the write enable latch (WEL) bit.
The PAGE PROGRAM command is entered by driving chip select (S#) LOW, followed by
the command code, three address bytes, and at least one data byte on serial data input
(DQ0).
If the eight least significant address bits (A7-A0) are not all zero, all transmitted data that
goes beyond the end of the current page are programmed from the start address of the
same page; that is, from the address whose eight least significant bits (A7-A0) are all
zero. S# must be driven LOW for the entire duration of the sequence.
If more than 256 bytes are sent to the device, previously latched data are discarded and
the last 256 data bytes are guaranteed to be programmed correctly within the same
page. If less than 256 data bytes are sent to device, they are correctly programmed at the
requested addresses without any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the PAGE PROGRAM command to
program all consecutive targeted bytes in a single sequence rather than to use several
PAGE PROGRAM sequences, each containing only a few bytes.
S# must be driven HIGH after the eighth bit of the last data byte has been latched in.
Otherwise the PAGE PROGRAM command is not executed.
As soon as S# is driven HIGH, the self-timed PAGE PROGRAM cycle is initiated; the cy-
cles's duration is t
PP
. While the PAGE PROGRAM cycle is in progress, the status register
may be read to check the value of the write in progress (WIP) bit. The WIP bit is 1 during
the self-timed PAGE PROGRAM cycle, and 0 when the cycle is completed. At some un-
specified time before the cycle is completed, the write enable latch (WEL) bit is reset.
A PAGE PROGRAM command is not executed if it applies to a page protected by the
block protect bits BP2, BP1, and BP0.
Figure 16: PAGE PROGRAM Command Sequence
7 8 C
x
0
C
MSB
DQ[0]
LSB
Command
A[MAX]
A[MIN]
MSB
D
IN
D
IN
D
IN
D
IN
D
IN
LSB
D
IN
D
IN
D
IN
D
IN
Note:
1. Cx = 7 + (A[MAX] + 1).
M25P128 Serial Flash Embedded Memory
PAGE PROGRAM
CCMTD-1718347970-10412
m25p_128.pdf - Rev. A 11/16 EN
26
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
SECTOR ERASE
The SECTOR ERASE command sets to 1 (FFh) all bits inside the chosen sector. Before
the SECTOR ERASE command can be accepted, a WRITE ENABLE command must have
been executed previously. After the WRITE ENABLE command has been decoded, the
device sets the write enable latch (WEL) bit.
The SECTOR ERASE command is entered by driving chip select (S#) LOW, followed by
the command code, and three address bytes on serial data input (DQ0). Any address in-
side the sector is a valid address for the SECTOR ERASE command. S# must be driven
LOW for the entire duration of the sequence.
S# must be driven HIGH after the eighth bit of the last address byte has been latched in.
Otherwise the SECTOR ERASE command is not executed. As soon as S# is driven HIGH,
the self-timed SECTOR ERASE cycle is initiated; the cycle's duration is t
SE
. While the
SECTOR ERASE cycle is in progress, the status register may be read to check the value of
the write in progress (WIP) bit. The WIP bit is 1 during the self-timed SECTOR ERASE
cycle, and is 0 when the cycle is completed. At some unspecified time before the cycle is
completed, the WEL bit is reset.
A SECTOR ERASE command is not executed if it applies to a sector that is hardware or
software protected.
Figure 17: SECTOR ERASE Command Sequence
7 8 C
x
0
C
MSB
DQ0
LSB
Command
A[MAX]
A[MIN]
Note:
1. Cx = 7 + (A[MAX] + 1).
M25P128 Serial Flash Embedded Memory
SECTOR ERASE
CCMTD-1718347970-10412
m25p_128.pdf - Rev. A 11/16 EN
27
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.

M25P128-VME6GB

Mfr. #:
Manufacturer:
Micron
Description:
IC FLASH 128M SPI 54MHZ 8VDFPN
Lifecycle:
New from this manufacturer.
Delivery:
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