TC58NVG1S3ETAI0
2012-09-01C
1
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
2 GBIT (256M × 8 BIT) CMOS NAND E
2
PROM
DESCRIPTION
The TC58NVG1S3E is a single 3.3V 2 Gbit (2,214,592,512 bits) NAND Electrically Erasable and Programmable
Read-Only Memory (NAND E
2
PROM) organized as (2048 + 64) bytes × 64 pages × 2048blocks.
The device has two 2112-byte static registers which allow program and read data to be transferred between the
register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single block
unit (128 Kbytes + 4 Kbytes: 2112 bytes × 64 pages).
The TC58NVG1S3E is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
• Organization
x8
Memory cell array 2112 × 128K × 8
Register 2112 × 8
Page size 2112 bytes
Block size (128K + 4K) bytes
• Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read
• Mode control
Serial input/output
Command control
• Number of valid blocks
Min 2008 blocks
Max 2048 blocks
• Power supply
V
CC
= 2.7V to 3.6V
• Access time
Cell array to register 25 μs max
Serial Read Cycle 25 ns min (CL=100pF)
• Program/Erase time
Auto Page Program 300 μs/page typ.
Auto Block Erase 2.5 ms/block typ.
• Operating current
Read (25 ns cycle) 30 mA max.
Program (avg.) 30 mA max
Erase (avg.) 30 mA max
Standby 50 μA max
• Package
TSOP I 48-P-1220-0.50 (Weight: 0.53 g typ.)
