TC58NVG1S3ETAI0
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(2) Multi Page Read with Data Cache
When the block address changes (increments) this sequenced has to be started from the beginning.
The sequence of command and address input is shown below.
Same page address (PA0 to PA5) within each district has to be selected.
BY/RY
60
Command
input
Page Address
PA0 to PA16
(Page m0 ; District 0)
tR
Address input
60
Page Address
PA0 to PA16
(Page n0 ; District 1)
Address input
30
A
A
BY/RY
00
Command
input
Column + Page Address
CA0 to CA11, PA0 to PA16
(Page m0 ; District 0)
Address input
05
Column Address
CA0 to CA11
(District 0)
Address input
E0
B
A
A
Data output
BY/RY
00
Command
input
Column + Page Address
CA0 to CA11, PA0 to PA16
(Page n0 ; District 1)
Address input
05
Column Address
CA0 to CA11
(District 1)
Address input
E0
B
B
Data output
(District 0)
(District 1)
31
C
C
BY/RY
00
Command
input
Column + Page Address
CA0 to CA11, PA0 to PA16
(Page m63 ; District 0)
Address input
05
Column Address
CA0 to CA11
(District 0)
Address input
E0
D
C
C
Data output
BY/RY
00
Command
input
Column + Page Address
CA0 to CA11, PA0 to PA16
(Page n63 ; District 1)
Address input
05
Column Address
CA0 to CA11
(District 1)
Address input
E0
D
D
Data output
(District 0)
(District 1)
3F
B
Return to A
Re
p
eat a max of 63 times
tDCBSYR1
tDCBSYR1
D
TC58NVG1S3ETAI0
2012-09-01C
35
(3) Notes
(a) Internal addressing in relation with the Districts
To use Multi Page Read operation, the internal addressing should be considered in relation with the District.
The device consists from 2 Districts.
Each District consists from 1024 erase blocks.
The allocation rule is follows.
District 0: Block 0, Block 2, Block 4, Block 6,···, Block 2046
District 1: Block 1, Block 3, Block 5, Block 7,···, Block 2047
(b) Address input restriction for the Multi Page Read operation
There are following restrictions in using Multi Page Read;
(Restriction)
Maximum one block should be selected from each District.
Same page address (PA0 to PA5) within two districts has to be selected.
For example;
(60) [District 0, Page Address 0x00000] (60) [District 1, Page Address 0x00040] (30)
(60) [District 0, Page Address 0x00001] (60) [District 1, Page Address 0x00041] (30)
(Acceptance)
There is no order limitation of the District for the address input.
For example, following operation is accepted;
(60) [District 0] (60) [District 1] (30)
(60) [District 1] (60) [District 0] (30)
It requires no mutual address relation between the selected blocks from each District.
(c) WP signal
Make sure WP is held to High level when Multi Page Read operation is performed
TC58NVG1S3ETAI0
2012-09-01C
36
Auto Page Program Operation
The device carries out an Automatic Page Program operation when it receives a "10h" Program command
after the address and data have been input. The sequence of command, address and data input is shown below.
(Refer to the detailed timing chart.)
Random Column Address Change in Auto Page Program Operation
The column address can be changed by the 85h command during the data input sequence of the Auto Page Program
operation.
Two address input cycles after the 85h command are recognized as a new column address for the data input. After
the new data is input to the new column address, the 10h command initiates the actual data program into the
selected page automatically. The Random Column Address Change operation can be repeated multiple times within
the same page.
80h
Page N Col. M
85h Din Din 10h Status Din Din Din Din
Col. M’
Din Din 70h
Busy
Data input
Selected
page
Readin
g
& verification
Program
Col. M Col. M’
The data is transferred (programmed) from the Data Cache via
the Page Buffer to the selected page on the rising edge of
WE
following input of the “10h” command. After programming, the
programmed data is transferred back to the Page Buffer to be
automatically verified by the device. If the programming does not
succeed, the Program/Verify operation is repeated by the device
until success is achieved or until the maximum loop number set in
the device is reached.
Selected
page
Program
Data input
Read& verification
CLE
80h
ALE
I/O
Page P
CE
WE
Col. M
Din
10h
70h
Din Din
Din
Data
Status
Out
RE
BYRY/

TC58NVG1S3ETAI0

Mfr. #:
Manufacturer:
Toshiba Memory
Description:
NAND Flash 3.3V 2Gb 43nm SLC NAND (EEPROM)
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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