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TC58NVG1S3ETAI0

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P65
TC58NVG1S3ETAI0
2012-09-01C
4
VALID BLOCKS
SYMBOL PARAMETER MIN TYP. MAX UNIT
N
VB
Number of Valid Blocks 2008 ⎯ 2048 Blocks
NOTE: The device occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document.
The first block (Block 0) is guaranteed to be a valid block at the time of shipment.
The specification for the minimum number of valid blocks is applicable over lifetime
The number of valid blocks is on the basis of single plane operations, and this may be decreased with two plane
operations.
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL PARAMETER MIN TYP. MAX UNIT
V
CC
Power Supply Voltage 2.7 ⎯ 3.6 V
V
IH
High Level input Voltage 2.7 V ≤ V
CC
≤ 3.6 V Vcc x 0.8 ⎯ V
CC
+ 0.3 V
V
IL
Low Level Input Voltage 2.7 V ≤ V
CC
≤ 3.6 V −0.3* ⎯ Vcc x 0.2 V
* −2 V (pulse width lower than 20 ns)
DC CHARACTERISTICS
(Ta
=
-40 to 85
℃
, V
CC
=
2.7 to 3.6V)
SYMBOL PARAMETER CONDITION MIN TYP. MAX UNIT
I
IL
Input Leakage Current V
IN
= 0 V to V
CC
⎯ ⎯ ±10 μA
I
LO
Output Leakage Current V
OUT
= 0 V to V
CC
⎯ ⎯ ±10 μA
I
CCO1
Serial Read Current CE = V
IL
, I
OUT
= 0 mA, tcycle = 25 ns ⎯ ⎯ 30 mA
I
CCO2
Programming Current ⎯ ⎯ ⎯ 30 mA
I
CCO3
Erasing Current ⎯ ⎯ ⎯ 30 mA
I
CCS
Standby Current CE = V
CC
− 0.2 V, WP = 0 V/V
CC
⎯ ⎯ 50 μA
V
OH
High Level Output Voltage I
OH
= −0.1 mA Vcc – 0.2 ⎯ ⎯ V
V
OL
Low Level Output Voltage I
OL
= 0.1 mA ⎯ ⎯ 0.2 V
I
OL
(
BY/RY )
Output current of
BY/RY
pin
V
OL
= 0.2 V ⎯ 4 ⎯ mA
TC58NVG1S3ETAI0
2012-09-01C
5
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta
=
-40 to 85
℃
, V
CC
=
2.7 to 3.6V)
SYMBOL PARAMETER MIN MAX UNIT
t
CLS
CLE Setup Time 12 ⎯ ns
t
CLH
CLE Hold Time 5 ⎯ ns
t
CS
CE
Setup Time 20 ⎯ ns
t
CH
CE
Hold Time 5 ⎯ ns
t
WP
Write Pulse Width 12 ⎯ ns
t
ALS
ALE Setup Time 12 ⎯ ns
t
ALH
ALE Hold Time 5 ⎯ ns
t
DS
Data Setup Time 12 ⎯ ns
t
DH
Data Hold Time 5 ⎯ ns
t
WC
Write Cycle Time 25 ⎯ ns
t
WH
WE High Hold Time 10 ⎯ ns
t
WW
WP High to WE Low 100 ⎯ ns
t
RR
Ready to RE Falling Edge 20 ⎯ ns
t
RW
Ready to WE Falling Edge 20 ⎯ ns
t
RP
Read Pulse Width 12 ⎯ ns
t
RC
Read Cycle Time 25 ⎯ ns
t
REA
RE Access Time ⎯ 20 ns
tCEA
CE Access Time ⎯ 25 ns
t
CLR
CLE Low to RE Low 10 ⎯ ns
t
AR
ALE Low to RE Low 10 ⎯ ns
t
RHOH
RE High to Output Hold Time 22 ⎯ ns
t
RLOH
RE Low to Output Hold Time 5 ⎯ ns
t
RHZ
RE High to Output High Impedance ⎯ 60 ns
t
CHZ
CE High to Output High Impedance ⎯ 20 ns
t
CSD
CE High to ALE or CLE Don’t Care 0 ⎯ ns
t
REH
RE High Hold Time 10 ⎯ ns
t
IR
Output-High-impedance-to- RE Falling Edge 0 ⎯ ns
t
RHW
RE High to WE Low 30 ⎯ ns
t
WHC
WE High to
CE
Low 30 ⎯ ns
t
WHR
WE High to RE Low 60 ⎯ ns
t
R
Memory Cell Array to Starting Address ⎯ 25 μs
t
DCBSYR1
Data Cache Busy in Read Cache (following 31h and
3Fh)
⎯ 30 μs
t
DCBSYR2
Data Cache Busy in Page Copy (following 3Ah) ⎯ 35 μs
t
WB
WE High to Busy ⎯ 100 ns
t
RST
Device Reset Time (Ready/Read/Program/Erase) ⎯ 6/6/10/500 μs
*1: tCLS and tALS can not be shorter than tWP
*2: tCS should be longer than tWP + 8ns.
TC58NVG1S3ETAI0
2012-09-01C
6
AC TEST CONDITIONS
CONDITION
PARAMETER
V
CC
: 2.7 to 3.6V
Input level V
CC
− 0.2 V, 0.2 V
Input pulse rise and fall time 3 ns
Input comparison level Vcc / 2
Output data comparison level Vcc / 2
Output load C
L
(100 pF) + 1 TTL
Note: Busy to ready time depends on the pull-up resistor tied to the BY/RY pin.
(Refer to Application Note (9) toward the end of this document.)
PROGRAMMING AND ERASING CHARACTERISTICS
(Ta
=
-40 to 85
℃
, V
CC
=
2.7 to 3.6V)
SYMBOL PARAMETER MIN TYP. MAX UNIT NOTES
t
PROG
Average Programming Time ⎯ 300 700 μs
t
DCBSYW1
Data Cache Busy Time in Write Cache (following 11h) ⎯ ⎯ 10 μs
t
DCBSYW2
Data Cache Busy Time in Write Cache (following 15h) ⎯ ⎯ 700 μs (2)
N Number of Partial Program Cycles in the Same Page ⎯ ⎯ 4 (1)
t
BERASE
Block Erasing Time ⎯ 2.5 10 ms
(1) Refer to Application Note (12) toward the end of this document.
(2) t
DCBSYW2
depends on the timing between internal programming time and data in time.
Data Output
When tREH is long, output buffers are disabled by /RE=High, and the hold time of data output depend on tRHOH
(22ns MIN). On this condition, waveforms look like normal serial read mode.
When tREH is short, output buffers are not disabled by /RE=High, and the hold time of data output depend on
tRLOH (5ns MIN). On this condition, output buffers are disabled by the rising edge of CLE,ALE,/CE or falling
edge of /WE, and waveforms look like Extended Data Output Mode.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P65

TC58NVG1S3ETAI0

Mfr. #:
Buy TC58NVG1S3ETAI0
Manufacturer:
Toshiba Memory
Description:
NAND Flash 3.3V 2Gb 43nm SLC NAND (EEPROM)
Lifecycle:
New from this manufacturer.
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