TC58NVG1S3ETAI0 Datasheet TC58NVG1S3ETAI0 | P28-P30

TC58NVG1S3ETAI0

2012-09-01C

Schematic Cell Layout and Address Assignment

The Program operation works on page units while the Erase operation works on block units.

A page consists of 2112 bytes in which 2048 bytes are

used for main memory storage and 64 bytes are for

redundancy or for other uses.

1 page = 2112 bytes

1 block = 2112 bytes × 64 pages = (128K + 4K) bytes

Capacity = 2112 bytes × 64pages × 2048 blocks

An address is read in via the I/O port over five

consecutive clock cycles, as shown in Table 1.

Table 1. Addressing

I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1

First cycle CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0

Second cycle L L L L CA11 CA10 CA9 CA8

Third cycle PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

CA0 to CA11: Column address

PA0 to PA16: Page address

PA6 to PA16: Block address

PA0 to PA5: NAND address in block

Fourth cycle PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8

Fifth cycle L L L L L L L PA16

2112

131072

pages

2048 blocks

2048

64 Page Buffe

Data Cache

I/O8

I/O1

64 Pages=1 block

8I/O

TC58NVG1S3ETAI0

2012-09-01C

Operation Mode: Logic and Command Tables

The operation modes such as Program, Erase, Read and Reset are controlled by command operations shown

in Table 3. Address input, command input and data input/output are controlled by the CLE, ALE,

CE , WE ,

RE and WP signals, as shown in Table 2.

Table 2. Logic Table

CLE ALE

CE WE RE WP

Command Input H L L H *

Data Input L L L H H

Address input L H L H *

Serial Data Output L L L H *

During Program (Busy) * * * * * H

During Erase (Busy) * * * * * H

* * H * * *

During Read (Busy)

* * L H (*2) H (*2) *

Program, Erase Inhibit * * * * * L

Standby * * H * * 0 V/V

H: V

, L: V

, *: V

or V

*1: Refer to Application Note (10) toward the end of this document regarding the WP signal when Program or Erase Inhibit

*2: If CE is low during read busy, WE and RE must be held High to avoid unintended command/address input to the device or

read to device. Reset or Status Read command can be input during Read Busy.

TC58NVG1S3ETAI0

2012-09-01C

Table 3. Command table (HEX)

First Cycle Second Cycle Acceptable while Busy

Serial Data Input 80 ⎯

Column Address Change in Serial Data Output 05 E0

Read with Data Cache 31 ⎯

Read Start for Last Page in Read Cycle with Data Cache 3F ⎯

Auto Page Program 80 10

Column Address Change in Serial Data Input 85 ⎯

Auto Program with Data Cache 80 15

80 11

81 15

Multi Page Program

81 10

Read for Page Copy (2) with Data Out 00 3A

Auto Program with Data Cache during Page Copy (2) 8C 15

Auto Program for last page during Page Copy (2) 8C 10

Auto Block Erase 60 D0

ID Read 90 ⎯

Status Read 70 ⎯ {

Status Read for Multi-Page Program or Multi Block Erase 71 ⎯ {

Reset FF ⎯ {

Table 4. Read mode operation states

CLE ALE

CE WE RE I/O1 to I/O8 Power

Output select L L L H L Data output Active

Output Deselect L L L H H High impedance Active

H: V

, L: V

HEX data bit assignment

(Example)

1 0 0 0 0 0 0 0

8765432I/O1

Serial Data Input: 80h

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57 P58-P60 P61-P63 P64-P65

TC58NVG1S3ETAI0

Mfr. #:

Buy TC58NVG1S3ETAI0

Manufacturer:

Toshiba Memory

Description:

NAND Flash 3.3V 2Gb 43nm SLC NAND (EEPROM)

Lifecycle:

New from this manufacturer.

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